Toshiba Electronics Europe will be providing details on its new packaging for its 4.5 kV class press-pack injection (PPI) enhanced gate transistor (IEGT) devices at PCIM 2018 in Nürnberg. The new packaging has been developed to further improve the rupture resistance of the device, thereby reducing the likelihood of damage to surrounding components and systems in the event of device failure.
The package is the result of research undertaken to evaluate the optimum volume ratio of materials in such packaging. Through experimentation the optimal ratio was determined where neither destruction of the ceramic, nor material leakage occurred. After careful measurement, the package was shown capable of withstanding 50 hours of short-circuit failure mode (SCFM).
The experiment was executed with one shorted IEGT chip, out of 42 IEGT chips, in a worse-case edge location. In addition, the rupture resistance tests, undertaken at a 3200 V test condition, resulted in 1.7 times higher resistance than that of standard PPI devices. The outcomes of the research will be presented at the PCIM Europe 2018 Conference by Raita Kotani and Georges Tchouangue on Thursday, 7th June at 11:15.
For more information visit www.toshiba.semicon-storage.com