With all of the buzz about wide-bandgap semiconductors like Silicon Carbide (SiC), and how it can improve your design, the main question for many is how to go about leveraging SiC’s performance benefits. Factors to consider are accurate test and measurement, optimizing the gate driver and integrating the gate driver loop with the power loop, among other things.
By Alix Paultre, Editor Power Electronics News (based on a technical paper presented by By Kevin Speer, Littelfuse)
The figure above shows a chart of the material properties of silicon, gallium nitride, silicon carbide, and diamond (just for comparison). The band gap determines a lot of the other properties on this table, like the highlighted breakdown field information. When you compare the breakdown field strength, it’s about 10 times larger for silicon carbide than Silicon. In silicon, when you go from about a 600V to 900V blocking rating to up to 1,000V and higher, the solution is usually an IGBT. In silicon carbide, because of the breakdown field strength, you can have a thinner voltage-blocking layer, and you can still use a majority carrier, or unipolar device. Again, for silicon, you have to go to bipolar.
The drawback of bipolar is when you inject these majority carriers, something has to happen to them when you turn the device off. They either have to recombine with the majority carriers, or they’re swept back across the junction where they came from. The drawback is both of these processes take time, and this is what creates your current tails or your reverse recovery occurs. This all leads to switching losses.
If you compare the switching losses of the silicon IGBT and a silicon carbide transistor, you get results something like this. This is hard-switching 400 volts and 100 amps. The switching frequency of 16 kilohertz. This is switching losses in millijoules versus the juncture temperature and between 100 and 150 degrees, which is where everyone uses their power devices, you’re almost entirely eliminating the switching losses when you use an IGBT if you go to silicon carbide. This is really the benefits and sort of the material physics as to why silicon carbide offers benefits over IGBTs.
Inductance triple threat
Getting into the meat of my talk a little bit. With the new technology like silicon carbide, there also can be new problems that we haven’t encountered yet, and I call this the inductance triple threat. You have three primary sources of inductance that cause problems in the behavior of your power circuit.
The first is the common source inductance, the coupled inductance between the gate source loop and the power loop. The second is the power loop inductance, the circuit through which the power switches themselves and the load. This is where that power flows, and can create major influences on voltage spikes and transients. The third one is the gate inductance, which can be either part of the package or a part of the total trace at layout.
One of the issues with silicon carbide becoming commercially mainstream in the past is there was a tendency on the part of manufacturers to make a device, and sort of throw it over the fence and say, “You guys figure out how to use it now.” A lot of problems that IGBTs didn’t have and silicon carbide does become design roadblocks.
The first of three challenges is accurate test and measurement. The basic principle here is if we have problems in our circuit because the devices are switching so quickly, if we can’t measure those problems, then how do we know it’s there? How can we fix it? What will happen is if we don’t recognize those problems because we couldn’t measure it accurately, we hope our customers put their products in the field when they have EMC issues, or there’s a failure of some sort. Measurement is not often talked about, but it is very, very important.
When it comes to switching speeds and flow rates, you see dV/dt five times faster with silicon carbide. These are just typical numbers. The IDT up to 10 times faster. Overall switching times are less than 30 nanoseconds, whereas, the IGBTs are usually north of 100 nanoseconds. With these fast switching speeds, we need to have high-performance measurement instrumentations, especially probes, that will capture these very high frequency dynamics.
When it comes to voltage, there are a few different methods that you can use to measure the voltage. The first is differential probes. There’s also sort of a rudimentary voltage divider. The final is passive probes.
All of these different techniques have their pros and cons, listed here. Passive probes offer the necessary bandwidth to capture the ultrafast dynamic nuances without the added bulk and parasitics of a voltage divider.
With respect to currents, there are four commonly used methods. There’s the current probe, the current transformer, the Rogowski coil, and the coaxial shunt. Again, all of them have their pros and cons. The really important part is to have a measurement technique that has very high bandwidth. This is not meant to optimize your system that you’re going to put in the field, but as you’re doing the design process, we recommend the coaxial shunt because it does has a very high bandwidth and high accuracy. The drawback to the coaxial shunt, of course, is it doesn’t have galvanic isolation, and it can also introduce some parasitics that will be undesirable if you were going to put that in your end system, and no one is going to have a coaxial shunt in their product that’s in the field.
The power loop
If you think about a power system, it really consists of two loops. The first is the gate source loop, and then, you have your power loop. Then there’s sort of this coupling or this marriage of the two loops, and that’s shown here by the common paths. Parasitic inductance as part of the power loop can include the package itself, like the pins on the package, the drain source or the drain pin, and the source pin. It could also include the overall parasitic inductance of the total trace, the busbars. When you have parasitic inductance in your power loop, this can lead to two prevailing problems.
The first, of course, is voltage overshoot, caused by a combination of parasitic inductance in the power loop, and also the speed at which your current is changing. Even at small values of power loop inductance, these voltage spikes can exceed the margin that design engineers build in, given the voltage overshoot and their voltage blocking rating of the device. What you have to do to compensate for these problems is either slow down the switching speed, which circumvents one of the benefits of silicon carbide, or select higher-voltage rated components, which are more expensive, or they go to more complicated topologies. These are some of the problems with voltage overshoot because of power loop inductance.
The second problem are switching oscillations. What this does, of course, is it generates electromagnetic interference. There are two ways in which the EMI can cause problems or wreak havoc in your system. There’s radiative coupling and also conductive coupling. Both of these types of coupling can creep into neighboring circuits, which can lead to malfunction of the protection or the gate drive. It can also have non-compliance with electromagnetic compatibility regulations. These are the two main problems associated with parasitic inductance in your power loop.
When it comes to optimizing power loop inductance,. The first is emphasize compactness and simplicity. Your board traces need to be short and/or as wide as possible. Another thing is to overlap the dc+ and dc- traces so that it’ll further reduce the inductance of your power loop. Finally, if you use a decoupling capacitor, it should be connected across the dc rails as close as possible to the power switches. What that will do is it will mask some of the high-frequency noise that’s created by the switches from creeping over and bleeding into the neighboring circuits.
The gate driver
When it comes to gate drive design and integration, the components of parasitic inductance, like the power loop inductance, can include the package as well, the gate pin, and the source pin. It can also include the overall parasitic inductance of the traces. With respect to the gate drive circuit itself, we typically want it to basically just do two things that are pretty trivial. Turn on and off the power switches in a very well-controlled, stable manner, and the other is to incorporate intelligent protection when necessary. It’s not asking much, but because of these parasitic components, there can be problems.
The first is gate voltage overshoot, usually due to a high parasitic inductance in the gate or the source paths. This is kind of like the voltage overshoot. It’s a combination of parasitic inductance with the rate of change. This can lead to inadvertent turn-on and catastrophic shoot-through failure. Also it can create excessive oxide fields. We’ve talked some about the sensitivity of the MOSFET gate oxide with these high gate voltages that it can induce some near-term damage and reduce the overall lifetimes of the device.
The second problem would be high inductance in the common source loop. What this does is it resists fast changes in the current and slows down the switching speed of your device, of your power system, and also unnecessarily, by virtue of that, increases your switching losses. Therefore we need to optimize the parasitic inductance components. As before, always try to follow the rules to reduce the length of the gate loop as much as possible, which will, in turn, reduce the magnitude of these gate source voltage oscillations. If you decouple the gate loop from the power source loop, it will reduce capacitive coupling, and minimize parasitic inductance.
The last thing is think orthogonally. In order to prevent near-field or radiative coupling of oscillations or EMI from the gate source loop bleeding into the power loop, you can often, when possible, place the gate source loop traces perpendicular to the traces to the bus-bar to the power loop. This will prevent a lot of the coupling that’s encountered.In summary, because of its mate
rial properties, silicon carbide is really poised to disrupt the entire power electronics community. But it’s incumbent on the device-makers to help customers overcome these challenges through improved measurement, precision, and accuracy, optimizing the power loop design, and also optimizing the gate drive design and its integration with the power loop.