The DC-DC Boost Converter, Part 3 – Power Supply Design Tutorial Section 5-3

This is the last part of the series dedicated to the boost converter, where we walk through the PCB layout for a medium power boost with a synchronous MOSFET at the output instead of the more traditional output diode. You don’t have to read sections 5-1 or 5-2 first to appreciate this part, but I do recommend it. 

  • PCB Layout for a DC-DC Boost Converter
    • A realistic schematic
    • Boost current loop analysis
    • The switch node goes first
    • The output capacitors
    • The input capacitors
    • Noisy and quiet sides of the control IC
    • Gate drives
    • Current sense lines
    • Power planes and four-layer treatment

In the following we’ll look at a realistic schematic for boost with all the components you haven’t seen in any of the simplified idealized schematics so far. I highly encourage all viewers to watch sections 3-1 and 3-2 of this webinar series before watching this one. These two parts present the theory behind PCB design for switchers. What follows is an analysis of the paths taken by the heavy currents into boost converter during its two switching states. Then the switch node, the output capacitors, the input capacitors and the control IC are placed in that order. Gate drives for the power FETs differential current sense lines and then the flooding of unused areas with power planes follow. The last part of section 5-3 explains how to take advantage of four-layer PCBs.

There is both art and science to PCB Layout. My goal is to convert you, my viewers, into electron whispers, or electron psychologists. Once you know why electrons do what they do, you’re well equipped to make them go where you want them to go, and that’s what PCB Design is all about.

The Sync Boost Schematic

Here’s the schematic for the circuit we’re going to layout. For a portable device it can put out a pretty decent amount of power, a peak of 30 Watts. The switching frequency is higher than usual, because this circuit needs to fit inside the handle of light saber. That’s right when I’m not designing power supplies, I spend my time defending peace and justice in the galaxy. The input to the circuit is two, 18, 600 sized lithium ion batteries. I break open the battery packs whenever a laptop computer dies and carefully, very carefully, save the batteries.

On more than one occasion the batteries caught on fire, which is why I officially recommend against doing this. Always buy properly designed battery packs with safety circuits. Power efficiency was a key for this design. So I used the synchronous bot controller. I probably gained around five percent efficiency by using the output MOSFET instead of a diode. Also included are two elements for switching edge control, which are a resistor in series with a boot strap pin to control the output MOSFET and a resistor in series with the gate of the control MOSFET. I start with zero ohm jumpers in these positions. Please see part four of this webinar series for lots of detail on this topic.

Boost Converter Current Loops

Every time you lay out a circuit board for a given topology, I recommend going through this current loop analysis. When doing so, I suggest including the input capacitors, which are sometimes omitted since they supply the AC portion of the input current, and its AC current that produces electrical noise.

When the control MOSFET is on the current, in blue, flows from the input and the input capacitor and flows through the boost inductor, causing the magnetic field to develop in storing energy. During this time the output capacitor is also hard at work, supplying all of the load current. When the control FET turns off the voltage across the inductor begins to rise. Remember that it’s capable, in theory, of going to infinity volts to maintain a constant current. Fortunately, it doesn’t have to go to infinity. As soon as the inductor voltage exceeds V out by more than a diode drop, the output diode forward biases. The current continues through the load, recharges the output capacitor and comes back to the source.

Now, let’s look at the circuit with both current loops. Any path with just one color is where heavy switched current flows. That means fast edges and high EMI. Naturally the MOSFET and diode are heavy switched currents, but the segment I want to draw attention to is the portion of ground that goes from the negative of the output capacitor back to the source the control FET. This part requires extra special attention.

One more thing before I move on. See how the current in the output capacitor reverses direction? That’s a clear indication that the output capacitor has suffered from heavy RMS ripple currents. 

Boost Converter Critical Area

When doing this presentation I used to refer to this area in green as a loop, but someone raised their hand during a presentation one time and said the current never flows in this path. And they were right. It’s the area enclosed by the two power switches and the output capacitor that needs to be minimized. That minimizes the inductance of the partial paths taken by current through the two power switches. And the lower the inductance, the lower the noise, both conducted and radiated.

Here’s a trick that’s not obvious but works very well. Even if you have a nice solid ground plane on the bottom layer, or on an internal layer, or both, don’t use those layers to connect the negative of the output capacitor back to the source of the MOSFET. Instead, use a big fat trace or copper shape on the same layer as the components. That’s usually the top layer. When you do connect to ground planes in other layers put the vias next to the negative terminal of the output capacitor. That way, the output capacitor, or capacitors can filter as much of the high frequency noise as possible before I get into the ground plane and contaminates everything.

Place the Power Switches and Inductor

I always start by placing the inductor and the two power switches. Here, Q4 is the low side control MOSFET and Q3 is the high side output MOSFET, both are QFN style power packages measuring 3×3 mm.

The big coper areas with four fingers are the drains where the majority of the heat escapes the packages. Q3 has it easy because it’s drain connects to the V-Out node and that will have nice, big copper areas to dissipate heat. Q4 is the big challenge, probably the biggest of the whole design because it’s drain and power pad connect to the switch node. On the one hand, you want to keep the area of the switch node to a minimum because both voltage and the current move up and down very quickly making this an antennae. Big antennae radiate more and we definitely do not want to hear the song this antennae is broadcasting over FM. I typically place a solid shape that just covers the pad of L1, the source of Q3, and the drain of Q4, but if the switch node copper area is too small, then Q4 will overheat. This can happen easily in boost converters because the control FET has the highest peak and RMS currents plus lots of switching loss. It’s a perfect storm for cooked MOSFETS.

Place the Output Capacitors

The second step in my boost layout is always to place the output capacitors. As we saw in slide six, the area enclosed by the two power switches and the output capacitors should be made as small as possible. That minimizes inductance. If you haven’t seen part three of this webinar dedicated the PCB layout, then you might be wondering why I seem to be anti-inductance. I’m not. I’m all for inductance when it’s in the right places. The reason I minimize inductance here is that the fast moving currents in the switch area generate voltage noise when they encounter inductance. Remember, V equals LDIDT. So, the higher the current, the higher the inductance or the shorter the time period, the more voltage noise is generated.

Pay special attention to C11 and C12. C11 is a small, low value MLCC of 100 nF. The low capacitance and the 0603 size package make it ideal for filtering higher frequency noise in the range where C12 is no longer capacitive. C12 is a 1210 sized, rated at 10 uF and should still be capacitive out to beyond 1 MHz, but C11 should stay capacitive out to beyond 10 MHz. The smallest caps go in toward the noise source, the switch node, so that they can do the best job possible of filtering the highest frequency noise.

Another note, my final design does have a so-called bulk cap, a 33 uF polymer aluminum device. Though not shown here, it would go to the right of C12. Since its job is not to filter high frequencies but to sustain the output voltage during low transience and to dampen any possible resonances between this boost and the next stage, a buck LED driver.

Place the Input Capacitors

Although I naturally don’t want to place my input capacitor or capacitors one meter away, you can see that this capacitor is a lot further away from the switch node than the output capacitors. That’s a perfectly acceptable compromise because the path and the source of Q4 back to the negative of C3 is high current, yes, but it’s a continuous current. Actually, it’s a triangle wave, and triangle waves certainly have harmonics, but the edges and RMS value are nothing compared to the up-loop trapezoid wave current.

R4 is another of those necessary evils, a current sense resistor. Often, you see this resistor placed in series with the source of the control FET where it dissipates less power, but makes the layout more difficult since it increases the area of a high DIDT path. Placed in series with the input, the current sense will be less noise, but dissipate more power since the full input current always flows through it. 

 Look at IC Pinout: Power vs. Signal

Most IC Pinouts are the results of collaboration between the IC designer, the IC layout engineer, and the applications engineer. Like the full external circuit, the internal circuit tries to group noisy pins that carry heavier switch currents on one side and sensitive circuits on the other side. Applications advises on what pinouts would make the external components easiest to place.

This chip here is a good example. Except for power good, which is a logic level signal, not essential of rhe system to work, everything needing high current is on the right, the switch node, TG, Boost, INTVCC, BG, and ground pins are the inputs and power rails for the MOSFET gate drivers. And although the average value of these currents rarely exceeds 20 million amps, there are peaks of multiple amps when using big FETS.

Clearly, they should be placed away from the sensitive, high impedance pins like the voltage feedback pin, VFB, the differential current sense pins, the soft start pin, SS, or the control loop compensation point, ITH. Sure enough, all those pins are on the left. 

Place the IC: Power vs. Signal Areas

With the IC Pinout in mind, it’s time to place it on the PCB. Most of the time, I orient the control with the noisy pins pointing towards the inductor and MOSFETS, but in this case, the PCB had to be long and thin, a maximum of 30 mm wide to fit inside the aluminum tube that makes up the hilt. Knowing that the input point is low noise, I set U2 as shown. Note that all the 0603 size components and the diode, D1, from the gate driving charge pump, or boot strap circuit, and also the decoupling for the output of the internal linear regulator and that powers the low side control FET gate drive. They are small components, but they are part of the high noise section.

All Components Placed

Here’s the first pass layout with all the components of this boost converter. Everything noisy is above or to the right. And everything sensitive is below and to the left. At this point, I usually put in the Vs I know are unavoidable like the gate drive ones for Q3 and Q4.

Right now it’s not obvious, but I’m going to use a top layer shape of ground to shield the control IC and the sensitive analog pins from electric field noise generated by the switching node. 

Route Switch Node with Solid Shape

Now that I’m beginning to actually connect the components, my attention turns back to the critical switch node. The copper shape on the top layer covers the pads of the three components, but does not extend much further. From experience, I know that this area of copper, even if it was 70 um thick, would probably not be enough to keep Q4 cool. So long before I get to the bottom side of the PCB, I put a nice array of thermal vias. My preferred dimensions are listed on the left. Holes of 0.25 mm and diameters of 0.5 mm. The dimensions of your thermals vias and how close they can get to the solder pads of the components is something that you need to discuss carefully with both your PCB manufacturer and your contract manufacturer.

If you’re like me and you use several different companies for both services, then talk to everyone. In my experience, vias sized to these dimensions can still be drilled with bits, not lasers and tat saves cost. But, the 0.25 mm hole is too small to join away a lot of the solder paste. If it did so, L1, Q3, and Q4 could all fail to connect properly. Rarely do they fail to connect electrically, but you want solid solder between the opening of your solder mask layer and the pad of the component. Any voids, meaning air bubbles, will increase the thermal resistance rapidly. That, in turn, leads to fried MOSFETS.

On the topic of good communication with your contract manufacturer, let’s talk about thermal relief for a moment. This makes mounting the components easier, but is absolutely terrible for both the electrical and the thermal performance of your PCB. It adds inductance, adds resistance, concentrates current in narrow passages and increases the thermal resistance. Do everything in your power to avoid routing with thermal relief. 

All Power Shapes Except GND

Here, we can see the remaining parts of the power path filled in with large shapes on the top layer. Often save ground until after much of the IC routing is done since this net also fills in a lot of otherwise unused PCB area. I find that once I give priority to the power path routing, my gate drive lines almost always have to go through the bottom layer. Multiple vias for connecting the gate drives is great for reducing parasitic inductance. Vias add a lot more inductance than you might think.

Here, although I had space at the gate pins of the FETS, I was squeezed for space next to the control IC. And since the power here’s not so high, I only put one via. 

Top Layer Power GND Shape

This is only part of the ground connection, but you can see how it acts as a shield for near FET electric noise. The most important part of this connection is from the negatives of C11 and C12 over to the source of Q4. That’s that portion where heavy switch currents flow. It’s an unfortunate fact of life that the gate drive pin and via make this path longer and more inductive. That’s a good example of the constant compromise made in all PCB layouts.

Output MOSFET Gate Drive

The first thing to talk about on this slide is the switch node. The bottom layer, in blue, has a shape as the same size as the top layer switch node shape and although thermal vias are used to double the mass of copper without doubling the area. Now there may be some air flow in the backside too even if only from convection and that will help to cool off poor Q4 as well.

This blue line shows the charging path of the floating output FET. Not shown in this diagram is the resistor in series with the boost pin that starts off as zero ohms so we’ll ignore it here. Then, the orange line shows the discharge path. Again, these paths can have peaks of amperes so the switch pin, the TG pins, should be routed as a differential pair, minimizing the inductions and therefore minimizing the induced voltage noise.

Slew Rate Control for Output MOSFET

When the prototype boards come back, I test everything with zero ohms in place of R12 as shown. I put the circuit at maximum output power, but, nominal input voltage that would be 7.2 volts for this circuit with the two lithium ion batteries in series. R12 and the boot strap capacitor, C9, are set in as tight a loop as possible. There mere existence of R12 makes this loop larger, but that’s a necessary compromise. Slowing the gate of the output FET works for the noise on the rising edge so I’ll still need to have some way to slow the low side control FET as well. As a final note, I did not include an RC snubber in this design, but if I wanted to control the falling edge ringing, the RC snubber would go in parallel with the output FET. If a blues converter needs such a snubber, it’s usually in parallel with the output switch, be it MOSFETS of diode.

Control MOSFET Gate Drive

There’s an important element here that’s not shown in the schematics that I took from the product data sheet, a gate resistor. It goes between the BG pin and the gate of the control FET. As with buck regulators, in most every case, it’s only the rising edge of the gate drive signal that we want to slow. And this gate resistor would also slow the falling edge, but there’s no boot strap circuit since this MOSFETS driver is ground referenced. It’s powered from the internal LEO INTVCC and I once thought to myself, hey, I could just put a resistor in series with INTVCC. But, that would make the LEO unstable and limit current to all the other internal circuits that draw power from INTVCC, so it wouldn’t work.

Instead, in cases where you need to slow the rising edge, but not the falling edge, the best solution to the small diode in parallel with the gate resistor with its anode at the gate of the MOSFET and its cathode at the BG pin. That way, the discharge of the gate capacitance is nearly unimpeded.

Current Sense Lines

You can see in this schematic here, that I did two things to help the layout engineer. Actually, I was the layout engineer, but the bigger the company, the more likely it is that one engineer draws the schematics, another designs the PCB. I’m also seeing more and more companies that use an external PCB layout service.

Now, usually, these services focus on digital boards with lots of layers. But, despite the fact that most things that work well for switchers also make sense for digital, many of the saddest layouts I see come from digital focused engineers. So, when lines need to be routed as differential pairs, I draw them close together in the schematic. Then, to erase any doubt, I write, differential pair. It only takes a minute to do and it’s very, very helpful. On my bottom layer sense lines could have been thinner. They only carry micro amps of current. And actually thinner is better because there’s less surface area and therefore less parasitic capacitance to noisy places. 

VIN and VOUT Sense

One thing that is often forgotten when sensing the input voltage or the output voltage in power supply designs is that even signals that are referenced to ground should still be run like differential pairs. Here, the V in sense line on the right and the V out sense line on the left only carry micro amps of signal current, but it’s still a current that must flow in a loop. The return path will be through ground. That’s one good reason why a nice continuous ground plane is so important. It lets the return currents of these voltage sense lines flow right next to the send paths.

Take a look at R5 and R6. These resistors set the DC value of the output voltage, usually they’re called the feedback resistors. One big error I still see quite a bit is putting them next to the output capacitors. They should go as close as possible to the feedback pin. The V out trace looks long and inductive, and it is, but it’s connected to V out with a mix of capacitors to provide low impedance over a wide frequency range. On the other hand, the trace from the tap between R5 and R6 and the feedback pin must be as short as possible because it’s very high impedance input to an amplifier, the air amplifier, and high impedances pick up noises far more easily.

R9 and R10 work in the same way. They set the under voltage lock out and they connect to the very high impedance input of a comparator, so they also go right next to the IC. The V in and V out sense lines can be long, but keep them away from the switch node and the inductor. Better to make them longer and give those noisy sources a wide berth

Signal Ground Trace/Shape

  1. Connect all the signal-level parts with GND together:
  2. Then connect to the GND pin, at only one point

This particular IC does not have a pin for the signal ground or analog ground. It just has one pin simply called GND and then it has a thermal tab that must be connected to ground electrically. In such cases, your ground shape connects to the power tab and the ground pin is shown by the blue error. From there, I recommend using a small shape or even a trace to connect all the other components that use the no noise signal ground. This green line here shows the trace. This is similar to a star ground approach and vias beneath the IC will connect to the ground plane or planes.

What I don’t like to see are vias to ground placed near each analog component because if heavy or noisy currents are flowing in the ground plane, the soft start capacitor, the feedback resistors, the compensation network and other things can see different voltages at their ground potential ends. 

All Electrical Connections Complete

Here’s the boost part of the circuit, all complete from an electrical perspective. That unconnected rat’s nest line you see goes to the buck LED driver that comes next.

This is a good time to point out the array of thermal vias at the negative of the output capacitors. Power comes into the circuit from the right, directly on the top layer and power flows out towards the left, also on the top layer. This means that heat flows down into the bottom layer, but noisy electrons should not. 

Floor Bottom Layer with GND

Unfortunately, after all the traces and vias, this ground layer looks a lot like Swiss cheese. Four layers would be better. I did add in an array of thermal vias for the IC here, but I’m not worried about noisy electrons getting under the IC since I provided them a much lower impedance path on the top layer.

The green line shows how the return current from the output voltage sense gets back to V out forming a loop. One compromise I made here is that the return path for the input voltage sense, well, it has to go around the via trace to get back to Vin. 

 Four Layer PCBs


Actually, I knew from the start that I would use four layers for this design. It also has quite a bit of digital circuitry and I knew I wanted to keep that separated. This is not to say that the PCB couldn’t be done in two layers, but when I compared the cost of four layers to the cost of many more hours of design time, plus the likelihood of more design revisions, the choice to use four layers was easy.

Whenever I route my power path components on the top layer, which is pretty much always, I then use layer two, also called mid-layer one in my routing software as ground. The reason is physical. There’s less distance between the top layer and mid-layer one so the beneficial parasitic capacitance is greater and the benefit of electric field shielding is better as well.

Only two things break the continuity of my layer two ground plane, vias, which are unavoidable, and a shape, identical in size to the top and bottom layer shapes, connected to the switch node. This is for thermal reasons. Again, more copper mass to help cool the drain of the control MOSFET. I have heard passionate arguments both for and against this technique with regards to EMC, meaning conducted and radiated noise. I don’t have a definitive answer about which is better right now, switch node cut outs or completely solid power and ground planes, I can say with confidence that this cut out technique has worked well fr me.

For layer 3 or mid layer 2, I once again dedicated a piece of the switch node, but then I divided the rest between V in and V out. Here, I kept V in and V out at the top and added more ground along the bottom. One thing that still gets me sometimes is the accidental shorting of the differential sense lines if the V in or V out power planes pass under the control IC.

Look at these two vias. The first is for V in for both the voltage sense and half of the differential input current sense. The second is for V out. If the V in or V out planes extended down to the IC, then these vias would be shorted out and all my efforts to run differential sense lines would be for nothing. This happens more often if you need an actual dedicated trace to send something ground referenced. In such cases, after I connect the V on the top layer, I usually place another via in the keep out layer on top. That generates a DRC error, but it prevents any planes or polygons from connecting to vias that you don’t want connected. Other than this, there are plenty of other ways to sort of trick your design software.

That concludes both section 5-3 and the whole series about Power Supply Design.

Link to previous section:  5-2 The DC-DC Boost Converter, Part 2




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