This is a continuation of Section 5-1, and I recommend reading section 5-1 before this one. It may also be useful to read section 2 on the buck converter for some background information that I don’t repeat here for the boost.
Section 5-2 Agenda
- Output capacitors – for steady state and for load transients
- Output capacitors: RMS currents
- Low-side (control) MOSFET selection – the three types of power loss
- Output diode selection – packaging and power loss
Section 5-2 continues the discussion of the power train components for a boost converter. We’ll start with plenty of detail for the output capacitors, looking at equations based upon steady state voltage ripple, and then based upon the response to load transients. Then, the RMS current calculations are discussed, also in detail, since these elements suffer lots of RMS current abuse.
Section 5-2 then moves onto the control MOSFET and its various types of loss and packaging. The last part of the power train, the output diode, is examined, exploring packaging options and power loss.
The output capacitors in a boost regulator are victims of high RMS current, much like the input capacitors to a buck or the input and output capacitors in a flyback regulator. Therefore, even though voltage ripple is an important spec, precise calculation of the RMS current is just as important, especially when aluminum, tantalum or other technologies are used that have lower RMS current handling abilities.
- Like the input caps, this is usually more than one individual capacitor
- High RMS currents mean that aluminum or tantalum caps can be used, but will need MLCCs in parallel
- Pure MLCC output caps are often enough when there are no load transients
There are two possibilities for the output capacitors in a boost regulator for a modern design. This bank of capacitors is either comprised of nothing but multilayer ceramics, or MLCCs, or it’s a mixture of MLCCs and other technologies that provide more capacitance, but have other drawbacks. I refer to these as buck capacitors.
Aluminum electrolytics, dry tantalum, polymer aluminum and polymer tantalum are the four most common buck capacitors. Together, this mix provides low impedance over a wide range of frequency.
Measuring Output Diode Current in Lab
To calculate the RMS current in the output capacitors, we need to measure or calculate the current in the output diode, which is a trapezoid wave with very heavy RMS content. Like the other power switches and the input capacitors, trying to measure the actual diode current causes a lot of problems.
First, a loop of wire for the current probe would add lots of inductance and alter the circuit operation. Second, most modern packages are surface mount, like this one here, and lifting it off the PCB will increase the thermal resistance so much that the diode would almost certainly overheat, more of that magic smoke escaping.
Measuring Output MOSFET Current in Lab
Here, I show a synchronous boost with my current favorite MOSFET package, the Thermal Enhanced SO-8. There’s no realistic way to lift this package off the PCB and get a loop of wire in series. Putting a current sensor resistor isn’t going to help either. That will still separate the drain, this big area connected with the thermal tab, from the PCB. The PCB is, of course, the heat sync and the MOSFET would surely burn up.
The good news here is that the output switch current is the same as the boost inductor current while the switch conducts. That means that we can see both the peak and the valley on a real oscilloscope. We just have to imagine that the current is zero while the control switch is on.
Defining Each Output Cap Current
Kirchhoff’s current law says that if we know two of the three currents entering a node, we can calculate the third. Looking in detail at the juncture of the output diode, or FET, the combined bank of output capacitors and the load, we can either simulate ID or measure inductor current and infer its wave shape. We know the load current from the basic specifications of the converter. With these values, we can calculate ICO, the total current flowing through the bank of output capacitors.
Defining Output Diode Currents
You might have noticed that the quantity I call ID-AVG is also the average inductor current. It’s also the average input current. It follows that ID-PK is also the peak conductor current.
Another thing to note is that the quantity T-OFF, referring to the fact that the control MOSFET is off, is equal to TSW, the switching period, multiplied by the quantity of 1-D where D is the duty cycle.
Calculate Total Output Cap RMS Current
Once you know the peak, the valley and the duty cycle of a trapezoid wave, calculating the RMS value is easy. I like to use Mathcad for my spreadsheets, but Excel works just fine as well as almost any other calculation tool that you like. Calculating the RMS current in the output diode isn’t just a step on the path to calculating the output capacitor, RMS current. We’ll also use the diode current to calculate how much it heats up.
My expression for the total RMS current and the bank of output capacitors assumes that the output current is purely DC, and that isn’t true. Flip back to slide four, and you’ll see that there is an AC portion as well. The reason I make this assumption is that it can be quite difficult to predict the output current wave shape. Many times, you simply don’t know the impedance of the load. The result of that is that my expression for ICO-RMS comes out higher than real life, because the RMS value of the output current is higher than its average value. I’m perfectly okay with that, since it causes a slight over design, and I call that engineering margin.
Output Capacitors RMS Current Split
These first order equations are not very accurate. For me, that means they’re usually off by more than 10%. As with the input caps and buck convertors, the different types of impedance between buck caps, where ESR and ESL dominate, and MLCCs, where reactants dominates, means that simulation is much better. Still, a simulation isn’t always available or making one may take too much time. It’s good to have at least some basic mathematical expressions.
Simulation + Comparison to Lab
Recall that a well-designed bank of capacitors, be they input or output capacitors and regardless of the topology, has the job of supplying or draining as much of the AC portion of the current as possible. Here, in this plot, the difference between the output diode current in blue and the total capacitor bank current in red is equal to the output current. That’s why the two wave forms have nearly the same wave shape.
One nice thing that simulators can do is calculate RMS values, which is great for checking the equations. In this simulation, the diode has to handle 3.6 amps of RMS current, which is quite a bit. It will need a good package with good heat syncing in real life.
I created this plot in LTspice to make my point, again, about inductor current in green being equal to diode current in blue, while the diode is on. If you have a current probe, and I certainly hope you do, then you can measure the inductor current and trust the diode current can be correctly inferred from it. Actually, you can also infer the control MOSFET current from the diode current, and that’s very helpful as well.
Output Capacitance 1: Steady State ΔvO
Okay, so we’ve carefully calculated and checked the RMS currents that the combined set of output capacitors will have to handle. Now, it’s time to see how much actual capacitance is needed. Once again, we use a maximum allowable voltage delta to determine the minimum output capacitance and steady state. This equation for capacitance is just the old I equals C dv dt rearranged.
Think of it as the load draining the output caps for a period of time equal to DMAX times the switching period. That factor of two is a so-called fudge factor, and is my own invention. Many different factors in real circuits contribute to voltage ripple being higher than calculated. Among them, the parasitic conductance and so, I double the calculated figure for some margin.
The same is true for the maximum ESR. I halve it because experience has taught me it’s useful to do so.
Calculating Output Voltage Ripple
This equation is not very accurate. Impedance of MLCCs is dominated by reactants, whereas impedance of buck cap is dominated by ESR. In fact, you’re probably noticing a trend. Every time a calculation requires the impedance of a capacitor, the calculations become inaccurate. This is one of the reasons that you often see spare footprints for capacitors at the inputs and outputs of switching regulators. Calculations are great, simulation is wonderful but, at the end of the day, you need to lab test to know the true voltage ripple. Many designs have a few spare footprints and if they’re not needed, well, they simply aren’t populated.
Having said that my equations aren’t very accurate, I have to say that even computer simulations aren’t very accurate unless they take into account the capacitance loss of MLCCs versus DC voltage, the capacitance loss versus various buck caps versus frequency and include estimations for ESL.
This section of an LTspice simulation shows the ESR but, as I’ve noted, I don’t really know the ESL for either the MLCCs or the volt capacitors. One thing I could have done was put both banks of capacitors, one at a time, into my network analyzer, which is also an LCR meter that produces a graph of impedance versus frequency. From that plot, I could have interpolated the ESL. In that same amount of time, I simply assembled the actual circuit and measured it with my oscilloscope.
Simulating Output Voltage Ripple
To give an example of simulation versus real life, here’s a plot of the output voltage ripple. 72 millivolts peak to peak is nice and low for a 34 volt output. That’s 0.2% peak to peak. Actually, since this is an LED driver, it’s really the output current ripple that has more value to our customer. However, conducted EMI standards for LED drivers do specify noise limits of the output ports. This voltage ripple does have some meaning.
Measuring Output Voltage Ripple
Here’s a plot of the actual circuit in the lab. The output delta is in blue at 20 millivolts per vertical division, and is about 80 millivolts peak to peak. Not too far off from the prediction in LTspice, but look at the wave shape. It’s quite a bit different. A question for you, why has the output ripple improved by only 20 millivolts peak to peak if the output capacitance was increased by nearly 100x? Answer, because at 370 kilohertz, the aluminum electrolytic cap has barely any capacitance left and has more ESR and ESL than the MLCCs.
Output Capacitance : for Load Transient
There’s a second criteria for selecting output capacitance that should be evaluated whenever you have a dynamic load. Examples of dynamic loads include just about anything digital, especially if it has active modes, sleep or shutdown modes or low power modes. Another example is LED drivers that dim by shutting the output on and off due to a PWM signal. Most of the time, your microcontroller or microprocessor will tell you, very explicitly, how much voltage [inaudible 00:09:00] they will tolerate when the load current transitions from low to high, or how much voltage overshoot they will tolerate when the load current transitions from high to low. That’s the deltaIload and the deltaVo-tran.
This voltage delta is normally greater than the steady state output voltage ripple. This boost regulator has a single 100nF comp cap – “slow but stable” – this explains the low phase margin and slow response. That explains the low phase margin and the slow response.
Any switching converter that delivers power to the output when the control switch is off has a troublesome aspect called a right-half plane zero in its small signal analysis. Boosts fall into this category. Recall that the inductor charges up when the control switch is on, then pumps current to the output when the control switch is off. You can find plenty of literature about right-half plane zeroes in the small signal domain, so here. I’ll simply say that they make it difficult to increase the controller bend when past a certain point. We can use this limitation to estimate the time domain response of a boost converter by, first, calculating the minimum right-half plane zero frequency.
Making the assumption that even a control loop guru would have trouble getting the total bandwidth beyond one quarter of the RHP zero frequency, let’s just calculate the minimum capacitance for load transience, as shown in the top equation. To be thorough, a second calculation for maximum ESR is included. In my experience, the maximum ESR calculation for steady state ripple almost always takes precedence. That means that it gives a lower maximum value for ESR.
After evaluating the two CO-MIN expressions and the two ESR-MAX expressions, pick the higher of the two for CO-MIN and the lower of the two for ESR-MAX.
Load Transient: DCM to CCM
In section 5-1, I talked about selecting inductance to keep a boost converter in CCM, and how it usually makes no sense to try and keep the converter in CCM down to very low output currents. You would need very high values of inductance. However, there are reasons to keep your supply in CCM down to reasonably low currents, and one of them is the transient response.
Compare this slide, which transitions from DCM to CCM and back again, to the response three slides back, which stays in CCM all the time. The current delta is about the same, one amp, but the voltage undershoot and overshoot are greater and the recovery times are longer here. I like to consider the time domain aspect of this. In DCM, the inductor current has drained all the way to zero. The magnetic field has also decayed to zero. When the system suddenly asks for more output current, it takes a finite amount of time to charge the inductor back up.
Balancing conduction loss and switching loss
There are still a few monolithic parts with internal power NPN BJTs and some very high power boost converters use IGBTs. The majority of external switch boosts use N-MOSFETs.
The main power MOSFET, or control MOSFET or low side MOSFET, should be the hottest part of your converter. If it isn’t, the design probably needs review. In boost converters, switching loss tends to dominate because the voltage slews back and forth from zero to V-OUT, and the current slews back and forth from zero to I-IN.
To get an idea of the current and the MOSFET for this scope shot, I took advantage of the current sensor resistor placed in the series with the source. Disregarding that big initial spike, which the control IC ignores, you can see the typical trapezoid shape. It’s not easy to see here, but the short periods where the current and voltage overlap are the times where switching loss occurs.
Low-Side FET Design Philosophy
For selecting an actual device, first, let’s do the easy part, the drain to source voltage. The maximum applied is V-OUT, so add around 20% for a safety margin. Drain current is another issue entirely. I never pay much attention to the maximum drain current specs. They’re tested at 25 °C, meaning an ideal infinite heat sync. Trust me, your PCB is not an infinite heat sync. The maximum drain current should, of course, be higher than the peak conductor current we calculated in part 5-1. In every design I’ve ever done, the datasheet spec was five or ten or 20 times higher.
The key, for me, is package selection and thermal management. I’ve stopped using TO-220 in my designs above 300 kilohertz due to the inductance in the leads. Instead, my current favorites are the Power SO-8 and the Power 3×3. These are QFN style packages with low lead inductance and good thermal paths with big power pads.
Control FET: Conduction Loss
I like to split the losses and the control FET into three main parts. Of these, conduction loss is easiest to calculate. It would be accurate if it wasn’t so difficult to determine the true RDSON of a FET. The trouble with RDSON comes from many things, but the main ones are, for one, RDSON changes with gate to source voltage. This is very important when pairing a control IC to the external MOSFET. Most modern controller ICs for just about any switching topology include MOSFET gate drivers. In most cases, the gate drive voltage is fixed.
It’s absolutely critical to use a MOSFET that has the RDSON and other characteristics specified for your gate drive voltage. It’s okay to have higher gate voltage, for example, a 6 volt gate drive for a logic level MOSFET specified at 4.5 volts is fine. If you paired a standard drive MOSFET, which needs 10 volts from gate to source, with only six volts of gate drive, the channel wouldn’t turn on all the way. The RDSON would be much higher than expected, and the MOSFET would likely burn.
Number two, RDSON changes in proportion to temperature. If a maximum value over temperature isn’t given in the data sheet, you can estimate it by multiplying the typical 25°C value by about 1.3.
Control FET: Switching Loss
Switching loss occurs for two main reasons:
- The rise and fall times of the voltage and current are not instantaneous. A good compromise between efficiency and EMC is usually in the range of 20 to 50 nanoseconds. During the overlap times, there is current flowing through the channel and voltage across it. Voltage times current is power.
- The parasitic capacitances of the MOSFET have to be charged and discharged each time they’re turned on or off. That takes energy. Energy divided by time is, once again, power.
This equation here is not accurate to actual switching losses, but it does serve to put in a spreadsheet and compare the relative losses of MOSFETs from the same manufacturer. The reason I say this is that different manufacturers specify their devices with different conditions making it quite difficult to say that two devices from two different suppliers, with similar characteristics on paper, are really the same. Lab testing is still the best way to find the best power MOSFETs.
Note that switching loss is proportional to switching frequency. Higher frequency means more current and voltage overlaps and more parasitic capacitance charges and discharges per unit time. This is the main reason that lower frequency circuits are more efficient.
Gate Charging Loss
Gate charging loss tends to be quite small compared to conduction loss and switching loss, but there’s a key difference. It occurs not in the MOSFET, but in the gate driver and that’s usually the control IC. More and more control ICs are available in packages with exposed power tabs or pads, but there are many older controllers that are still excellent parts. Their SOIC, or TSSOP packages, have thermal resistances that are on the order of 100°C/W.
A seemingly small amount of dissipation drives the gates of big FETs. It can overheat the controller. I don’t show it here, but the actual dissipation in most control SCs is actual equal to the input voltage multiplied by the total gate charge, and then multiplied by the switching frequency. That’s because most controllers have an internal linear regulator to generate VCC from V-IN. The same current needed to drive the FET, or FETs, also burns power dropping from V-IN to VCC. In conclusion, when you do your temperature testing, make sure to monitor your control IC as well as the power switches.
Totaling FET Losses and Checking TJ
In modern MOSFET packaging, bigger is not always better. When the package has a thermal tab, more copper area and more thermal vias are great. Both have that inverse exponential drop off, meaning that doubling the copper or doubling the number of vias is far better than just one, but 20 times that copper area or 20 times the number of vias provides diminishing returns.
Thermal vias need to be directly underneath the thermal pad to drain of the MOSFET in order to work best. That means talking to your PCB manufacturer and your contract manufacturer to find the best compromise of cost and manufacturer ability. My personal favorite size is a hole measuring 250 microns, or one quarter of a mm, with an outer via diameter of 500 microns. That’s ½ mm. I like to space them at least 1 mm apart.
Holes of 250 microns or below are less likely to wick, meaning drain away the solder on the thermal pad during assembly. This is essential since any voids, meaning air gaps between the thermal pad and the PCB, will make the thermal resistance of the MOSFET rise often dramatically.
Just five years ago, this part of the presentation would have focused exclusively on diodes. Power density improvements have changed things, and there are more and more control ICs and monolithic parts using MOSFETs for the output switch.
As a general rule, I use diodes for output currents up to two amps or so. In the range of two to four amps, both MOSFETs and diodes with big heat syncs are possible. Above four or five amps, I would only use a diode if no synchronous driver was available.
The average diode current is equal to the output current. The maximum reverse voltage is equal to the output voltage. Up to 100 volts DC of reverse blocking, I always select Schottky diodes for their low forward voltage drop, and their near zero reverse recovery loss. Schottkys are available up to 200 volts DC, but with a lot less selection. They also evaluate ultra-fast rectifiers for voltages above 100 volts. Above 200 volts, you can either use ultra-fast rectifiers or maybe even silicon carbide Schottkys, but that’s usually for AC to DC applications.
The voltage and current ratings for diodes are nice and straightforward. For the voltage rating, much like the MOSFET, I add 20% to the maximum output voltage giving me some margin for transience spikes etc. Unlike MOSFETs, the continuous current ratings for diodes are fairly trustworthy. I pick a diode whose current rating exceeds the maximum DC upper current by at least 20%.
Diode loss is assumed to be all forward conduction loss using the simple expression shown here. As usual, the complex part of thermal management is selecting the appropriate package, which is based on thermal resistance and PCB design. Some of the newer offerings, such as eSMP and the PowerDI5, not only have better thermal resistances and footprints similar to the SOD-123, or SMV respectively, but they also have lower inductance. You saw the trapezoid wave current with the sharp edges, so lower inductance is wonderful for EMC. Minimization of inductance is the reason I don’t suggest any through-hole leaded packages on this slide.
Next up: Section 5-3: PCB Layout for a DC-DC Boost Converter
In the next and final section dedicated to the boost converter, we’ll route the PCB for a 30 watts synchronous boost converter. The front end for my lightsaber, in fact. If you haven’t seen sections 3-1 to 3-2 , these are the ones dedicated to the theory of PCB layout. They make a good background for the step-by-step process to be followed in section 5-3.