Here is the agenda for Part 2-2 of our Power Supply Design Tutorial:

- RMS currents in buck input capacitors
- Total RMS current
- Split between MLCC and bulk capacitors

- Design philosophy and selection of output capacitors for buck regulators

As you can see, this part won’t cover many topics. First, the discussion on input capacitors will be finished. The input capacitors to a buck regulator are the unsung heroes of the design, at least in my opinion, and knowing with precision the RMS current that they endure is critical to a long service lifetime for your power supply. You might be surprised that the output capacitors actually get less time and attention, but it’s true. The output inductor means that they suffer a lot less RMS current stress, and that takes one factor out of their design equations, making them easier to select.** **

**Definition of Key Terms**

- Nominal input voltage, V
_{IN}, ex. 13.8V for passenger vehicles- Maximum input voltage, V
_{IN-MAX}, ex. 42V for a clamped load dump - Minimum input voltage, V
_{IN-MIN}, ex. 4.5V for start-stop

- Maximum input voltage, V
- Maximum output current / maximum load, I
_{O-MAX}/ R_{O-MIN} - Nominal Duty Cycle, D
_{NOM}, when input voltage is nominal- Maximum duty cycle, D
_{MAX}, when input voltage is at a minimum - Minimum duty cycle, D
_{MIN}, when input voltage is at a maximum

- Maximum duty cycle, D
- Multi-layer ceramic capacitors, MLCCs
- DC resistance, DCR, of inductors
- Equivalent series resistance, ESR, of capacitors
- Converter or regulator: switching IC with at least one internal power MOSFET
- Controller: switching IC with external power MOSFET(s)
- Module: switching control, power switches, inductor and passives in one package

**The Input Capacitors, Part 3: RMS Currents**

For this slide, I re-drew the input port of a buck converter to make a few points. The quantity I-IN is a high RMS, high harmonic content trapezoid wave equal to the input current when the control switch is on and equal to zero when the control switch is off. The job for CIN1, which represents all the MLCCs, and CIN2, which represents all the bulk caps or damping capacitors, is to smooth out that trapezoid wave, and does something as close to DC as possible for ISOURCE. That means handling a lot of RMS current, also called ripple current. The one that I’ve labeled I-CIN has the same wave shape as I-IN, but it’s centered around zero amps.

By their nature, capacitors don’t pass DC current, but they do pass plenty of ACR MIS current, and as it passes through their ESR it generates heat. As always, heat is enemy number one. MLCCs can cook away all day long without suffering, but we have to protect the aluminums or tantalums or they won’t last as long as the power supply needs to last.

Take a closer look at the point where I’ve labeled the input voltage ripple, delta V-IN. In theory, one could measure anywhere between the positive and negative terminals with the input capacitor bank, but in practice their inductance is between each actual capacitor. If we want to see all of the voltage noise, meaning the truest delta V-IN, we need to measure across the input capacitor that’s closest to the power switches. If those power switches are internal to the control IC, then the measurement is taken across the capacitor that’s closest to that IC.

**Capacitor Currents are Difficult to Measure**

To make a point, I stood the two MLCC input capacitors to a buck converter on end, and started a loop of wire in series big enough to fit my current probe into. I also tested that exact same loop of wire with my network analyzer, which doubles as an LCR meter. That’s an inductance capacitance and resistance meter. 50 nanohenries doesn’t sound like much, but it made a complete mess of the input port. That effectively raised the output impedance of the input filter. It made the circuit oscillate like crazy. This is the main reason that I don’t normally try to measure capacitor currents in the lab. To do so usually ruins the circuit operation.

**Calculating Input Capacitor RMS Current, 1**

Does this equation for source current look familiar? It should. I was calling it input current in the previous section. Now, we need to separate the concept of input current drawn by the switching cell and the current provided by the input power supply or battery or generator or solar cell, whatever energy source we’re using. Hopefully, seeing how badly this circuit reacts to having the input cap current measured directly has convinced you that trying to measure I-IN, the MOSFET current, would be a catastrophe. I’ve tried this, in fact, and what usually happens is that the added inductance slows down the switch so much that it melts, smokes, or blows up. I’ll give you a lot more detail on why a slow switch usually burns up in Section 2-3.

Instead of condemning a control switch to a fiery death, we can measure inductor current to check on the average and peak current values that are being calculated here.

Another important point, and one that confused me for a while, is the difference between DC input current and what I’m calling average current here. These quantities are not the same, and mixing them up will make all of the RMS calculations come out wrong. So called average current means the median height of the trapezoid waves. If they were square waves, it would be the height of the squares.

**Calculating Input Capacitor RMS Current, 2**

Remember that delta IL is the inductor ripple current, and that’s the same equation for inductance with the term simply rearranged. A trapezoid wave has a well-defined RMS equation, and that’s why we went to all the effort of calculating all of these quantities. This RMS equation is for the MOSFET current, so keep it in mind. It can be used later to estimate the temperature rise in the power MOSFET or, if using an ICU with an internal high side switch, the temperature rise with the IC.

As I’m sure you can imagine, the best use for these equations is in a spreadsheet since hand calculation would be a tedious task.

**Calculating Input Capacitor RMS Current, 3**

If you know two of the three currents entering or exiting a node, then Mr. Kirchhoff says that you can calculate the third current, and that’s exactly what we do here, except for RMS currents we use a sum of squares. I like this equation because it helps to make the point that the input cups filter out as much of the AC portion of the input current as possible, making the source current as close to DC as possible. That, of course, is best for EMC.

In practice, ISOURCE is not purely DC, but assuming that it is provides us with some engineering margin because it purposefully adds more delta into the input capacitor current, making its RMS calculation slightly higher than reality. All this is done in the name of a robust design.

**Simulating RMS Currents**

Here’s a simulation result showing what I’m calling the input current, or the MOSFET current trapezoid wave. The average value is nearly identical to the average value of the source current, but all that ripple makes the RMS value go way up. By the way, that’s one of the reasons that ripple currents and voltages are reduced as much as possible in power systems.

RMS is basically a measure of how much a current heats up whatever its passing through. We tend to think of a low ripple as being an issue for electromagnetic compatibility, but we also want to avoid hanging up the cables and the PCB tracers and everything else that carries power from one place to another. The motive is simple, less heat means better reliability and longer service lifetime for everything.

One thing I like about LTspice is that the RMS calculations are specific to the window you’re zoomed into. The complete plot from MOSFET current in this simulation included some big transients due to startup, especially when the input capacitor was initially charged up. Some simulation software makes it more difficult to calculate the RMS value of a subsection of the waveform. Transients and transient analysis are, of course, very important, but here we’re interested in steady state power dissipation. By the way, oscilloscopes with RMS calculations built in will naturally give you the RMS value of the portion of the signal you are observing on screen also.

**Grouping Capacitor Types**

A buck converter delivering more than a few watts of power usually has multiple capacitors of the same type in parallel. Trying to calculate the individual RMS currents for each device would be a nightmare. Instead, for calculation purposes, I suggest combining all the ceramic caps of the same type into a single device to represent the MLCCs, and then another device to represent all the parallel bulk caps. That simplifies things into just two parallel elements that will split the ripple current. If you have low value ceramics, like 1 microfarad, 100 nanofarads, etc., don’t bother including them in either of these conglomerates. They don’t matter for the calculations we’re going to do here.

**RMS Current: Split between Bulk and MLCC**

So far, we’ve calculated the total RMS current that the combined bank of input capacitors needs to withstand. The next important step is to make sure that the bulk, or the damping capacitors, aren’t being cooked by taking on too much for that ripple current. This is one instance where equations can really only go so far. These expressions calculate reactance and then impedance, but in reality the impedance of bulk aluminum capacitors, or tantalum or other bulk types, is dominated by their ESR, whereas the impedance of MLCCs is dominated by their reactance. These expressions are typically off by more than 10 percent from measured reality. Most of the other expressions shown in the seminar series are good to within about plus or minus five or plus or minus 10 percent. For this reason, RMS current split is one area where I like to use computer simulations.

**RMS Current Split: Simulation is Far Better**

- First order impedance equations are inaccurate
- Impedance of bulk types dominated by ESR, ESL
- Impedance of MLCCs dominated by capacitive reactance

PIDWebinar2-2-9_RMS Current Split Simulation is Far Better

The first thing you might say upon seeing this plot is, “Hey, why is that trapezoid wave turned upside down?” Remember that currents and voltages all have polarities that we assign as we please. The only thing is to make sure that we are consistent in the assignment of those polarities. This plot is from LTspice, and it comes out seemingly upside down because by default that software shows the currents from top to bottom to avert a clear lined element. This is the kind of plot I like to see. The blue waveform, MLCC ripple current, represents nearly all the total input capacitor bank ripple current. Since barely any current flows through the bulk caps, in red, they barely heat up. That means a long life and less evaporated electrolyte. Keep in mind that MLCCs size 1206 and 1210, which are my preferred sizes, can handle at least three amps RMS each. Actually, in real life there would be even less ripple current through the bulk caps because they’re really no longer capacitive at this frequency, which, by the way, is 500 kilohertz.

**Input Voltage Ripple: Proper Measurement**

In Section 2-1, I spent some time talking about the best way to make a current measurement. Now it’s time to talk about voltage measurements. Using the ground lead, or pigtail as we call it in English, that’s fine for quick checks of voltages where noise in the measurement isn’t a problem, but now it’s time to measure what my old colleague in the marketing department at National Semiconductor used to call a money spec. That means something that’s of genuine value to the customer.

Even if your buck converter isn’t connected to a [BUS 00:09:26] with a conducted EMC limit, you always want to minimize voltage ripple at the input and at the output. To measure properly, eliminate that ground lead and use the spring tip that came with your scope. “What’s that,” you say? Are you a junior engineer that inherited an old scope and all the accessories were lost back in 1987? No problem. You can make your own.

Take some solid wire of about 1 millimeter in diameter, that’s 18-20 gauge, and strip off about 10 centimeters of insulation. Now wrap that part that’s missing the insulation around the exposed barrel of the scope probe and bend the tip out 90 degrees, then another 90 degrees down. Both bends should be about 1 centimeter long. My low inductance test fixture is a section of 100 ml or 2.54 millimeter pitch breakaway header. Three or four sections work best. Cut out the center pins, then solder it right across the smallest MLCC that’s closest to the MOSFETs, or the IC if the switches are internal.

**Input Voltage Ripple – Two Parts**

This measurement was made using the low inductance technique I just described. When you minimize inductance, you know that most of the waveform you’re seeing is actual conductive signal, not noise coupling into the ground lead of the voltage probe. The blue arrow shows us the voltage of the input rail moving up and down at the switching frequency. If we took a frequency demand plot with a spectrum analyzer, we’d see a big spike at this frequency. A triangle wave is not as heavy in harmonic content as square waves or trapezoid waves, but there are still plenty of harmonics to deal with.

The white circle shows us the PARD noise. A switching converter, even a resident converter, has at least some high frequency noise that comes from the ringing of the switches turning on and off. That’s energy stored at the junctions of the semiconductors, and it resonates with stray inductance from the inductors and transformers, and with the parasitic capacitance of everything, but mostly the switches themselves.

PARD stands for periodic and random deviation, but in English, power supply engineers usually say spikes or junk, or other words that I can’t repeat in a seminar that is appropriate for all ages.

A really good quality power supply will have a spec for input voltage ripple and output voltage ripple that includes both the switching component and the PARD component, but most suppliers cut corners and list just the switching ripple.

**Input Voltage Ripple: PARD Spikes**

This is the same circuit, but zoomed in to show the frequency of the ringing. The noise is typically in the range of 50 megahertz to 500 megahertz. One way to distinguish between this ringing and DCM oscillation is frequency. DCM ringing should be 10 to 20 times lower. That’s because it’s due to the full inductance of a winding, not just a leakage. Most of the harmonic content of the switching frequency ripple dies down to below the EMC limits by around 10 megahertz for most switchers, so PARD noise, or spikes or rigging, show up as a new fundamental frequency with their own harmonics.

The majority of conducted EMI specs stop measuring conducted EMI at 30 megahertz, so most PARD noise is usually of a concern for the radiated emissions. Part 5 of the seminar series will focus on how to reduce and control ringing at the source. Be sure to watch that portion if you’re having trouble with radiated EMI.

**Range of MLCCs and Bulk**

This is the input capacitor bank for a serious buck converter, with a peak output power of 600 watts. C38 is for high frequency noise, and the power MOSFETs appear directly to the right of C38 in the complete schematic.

Then comes my solid bank of six identical 10 microfarad MLCCs. Each one can handle more than 3 amps of RMS current. The notes I write to myself explain that the actual capacitance when I apply 26 volts, 36 volts, or somewhere in between, gives me somewhere from 4 microfarads to 5.5 microfarads per cap. These notes are especially useful if the engineer who designs the schematic is not the same person who routes the PCB.

Keep in mind that smaller devices, for example 1206 sized MLCCs with the same 10 microfarad 50 volt X7R spec would lose more capacitance to the same DC voltage. 1812 sized capacitors would lose less capacitance.

Budget is one dictator of the capacitors used, but another thing to keep in mind is cracking. MLCCs are brittle. After all, they are ceramics. Unless a client specifically tells me it’s okay to use bigger ones, I don’t usually go bigger than 1210. The bulk cap C31 can go farthest away. It has no hope of responding to high frequency events, so having more inductance between it and the MOSFETs is no problem.

**Output Capacitors**

The output capacitors get most of the glory in any power supply. They are responsible for a money spec that’s even more important than input ripple, namely output voltage ripple, but compared to the input capacitors and buck regulators, these caps have an easy life.

I’ve repeated my technique here from the input caps and drawn two devices in parallel. The polarized one could be any of the technologies discussed at the end of Section 2-1, aluminum electrolytic, solid tantalum, polymer aluminum, polymer tantalum, even more exotic types like niobium. The non-polarized capacitor is, you guessed it, an MLCC.

The square wave shape of the output ripple indicates that ESL, that’s equivalent series inductance, contributes more to the impedance of the output caps than ESR does. If you stuff a triangle wave current into an inductor, the resulting voltage is an integral, a square wave. The quasi sinusoid shape in between the sharp edges indicates that capacitive reactance dominates the impedance. This square wave plus sinusoid-type shape is a clear indicator of purely ceramic output capacitors. If this was an aluminum or tantalum output cap, the ESR would dominate and the voltage waveform would be mostly triangular. Where it gets tricky to tell by way of shape alone is with the very low ESR polymer capacitors, but this isn’t an exam, so don’t worry.

FPGAs and microprocessors are notoriously picky about the tolerance of their output voltage ripple. Sometimes their specs are a real headache to interpret, but lately the manufacturers seem to have caught on to the importance of power supplies. It certainly took long enough. In any case, if you’re loading something fancy and digital, you probably know exactly what you need; otherwise, start with one percent to five percent and experiment.

The design philosophy based upon limiting ripple to a percentage of the DC value should be familiar by now. I’ve introduced two of my own fudge factors here. A fudge factor is something you add in without genuine scientific backing. It’s based upon experience and/or convenience. Like the ripple split with the input caps, it’s hard to predict total impedance for the different output capacitor types, and pretty much impossible when you’ve combined various types, so I’d double the minimum capacitance and halve the maximum ESR. Some of the things I’m fudging are for the tolerance of capacitance and ESR, but also for the presence of ESL, that sneaky parasitic inductance that almost never gets specified, but it contributes to a very real voltage delta in the presence of an AC current.

The second major factor that determines the minimum output capacitance is the response to load transients. To be clear, a load transient means a sudden shift in output current. It could also be a sudden shift in output resistance or even output voltage, but current is the most common type. Most load transients occur much faster than the control loop can respond, so the converter depends upon the output capacitors to hold up the output voltage as that extra current is being drawn. Again, fancy digital loads will usually stay with great precision the shift in voltage that they tolerate during their maximum load transient. Sometimes that’s added to the steady state voltage ripple. Sometimes there’s a given budget in the combined steady state ripple and load transient delta have to share. In general, you will need more capacitance for load transients than you will for steady state ripple alone.

- The factors of 2 in each equation form an assumption that voltage drop across ESR and capacitive discharge each contribute one-half of the total voltage transient
- Select actual output capacitance to be higher than the greater of C
_{O-MIN1}and C_{O-MIN2} - Select actual total ESR to be lower than the lesser of ESR
_{MAX1}and ESR_{MAX2}

Here in these equations, you’ll see more of my own personal fudge factors. The reasons are the same. If you go back to those plots of capacitance in ESR versus frequency for the various capacitor types, those are in Section 2-1, it’s quite clear that you rarely get all the capacitance you want, especially over frequency, or an impedance as low as you would like if you put only the bare minimum amount of capacitance or have just barely less than the maximum amount of ESR you calculated.

These equations are a similar philosophy to the steady state output capacitance calculations. They attempt to determine how much capacitance is needed to keep the output voltage from drooping too much during a given period of time. That’s one switching period for steady state ripple voltage and for load transients it’s the time that it takes for the control loop to respond. This time is variable, but it’s always longer than a single switching cycle.

It’s also worth noting that the same capacitance is needed to absorb current when there is an unloading transient, meaning that the load suddenly shifts from heavy to light. Digital loads do this all the time naturally. When current goes up, it has to come down.

As a final note, the design philosophies I present in this seminar are not the only ways to pick components for power supplies. There are plenty of other ways to do this. These are conservative design guides aimed to get you a working design early on, with room for refinement later.

While discussing the input capacitors, I stated that equations attempting to predict the overall impedance of a bank that mixes different capacitor types are usually inaccurate. By inaccurate, I mean off by more than 10 percent from actual lab measurements. That holds true for these output impedance measurements as well. The delta V out calculated here is a figure to start from, but I can’t stress enough how important it is to actually lab test switching inverters, and this is one reason why.

When actually testing, as long as you select a total capacitance that’s higher than the greater of the two calculations for C out minimum, and as long as your ESR is less than the lower of these two calculations, then the steady state ripple should meet or be lower than your target, and the delta during low transient should also be lower. The biggest unknown that may cause trouble is the ESL, that parasitic inductance. Once again, a lab test is of utmost importance.

**The Complete Output Capacitor Bank**

To conclude our discussion of output capacitors, let’s look at a practical complete output capacitor bank. This blend of capacitors provide low output voltage ripple that’s delta VO in steady state thanks to the two MLCCs, C out 1 and C out 2. For this 5 volt output, I put the highest value ceramics I could find with an X7R dielectric and 10 volt rating in 1206 footprints. The two 330 microfarad polymer tantalum capacitors, C out 3 and C out 4, weren’t very capacitive at 500 kilohertz, which is the switching frequency, but their high capacitance and low ESR allows them to respond to load transients and sustain the output voltage. It would take eight or more MLCCs to do that job otherwise.

Finally, although I haven’t loaded it in this case, the footprint for C out 6 would be perfect for a low value MLCC, for example 100 nanofarads or 1 microfarad. It’s job would be to filter out those PARD spikes, that’s the high frequency ringing, before they could get into the output cabling, where they would radiate EMI. Don’t forget to use the low inductance spring tip for the ground lead, as I’ve shown here. The delta V out measurement should always be taken with this technique and done right between the output posts or, if the load is on the same PCB, right across that last output capacitor, C out 6.

** ****Next Up: Section 2-3 – Buck Converters, final part**

Section 2-3 is the final part for the bulk converter, where we’ll look again in some detail at the control switch or high side switch. The types of discrete switch are almost exclusively MOSFETs, so the loss calculations, packaging overview, and gate control focus on this type of switch. For low side switches we’ll discuss diodes, usually used at high duty cycles and lower currents, or synchronous MOSFETs, which are exclusively n-MOSFET type. These are used for lower duty cycles and/or higher output currents. Then, we’ll examine the pros and cons of placing MOSFETs in parallel and discuss why diodes are not used in parallel.

The final part of Section 2-3 will look at the clocking in switches and how this can benefit both the time domain and frequency domain characteristics of switches.

That concludes Section 2-2. You’ve now seen two-thirds of our deep dive into buck regulators. Once again, I’d like to thank Power Electronics News for giving me the chance to present this webinar series. I look forward to seeing all of you, virtually at least, for Section 2-3.

**Link to next section: 2-3 Buck Converter, Part 3**

**Link to previous section: 2-1 Buck Converter, Part 1**

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