Welcome to section, 3-3 of our Power Supply Design Tutorial. If you have seen yet parts 3-1 and 3-2, I strongly encourage you to do so. Since this section takes all the theory discussed in the previous two, it represents a step-by-step application of it all for a practical PCB design.
In this final section on PCB layout, we’re going to look at reduced schematics from the mocking department as compared to practical ones. I’m gonna start with the challenge of the switch node. From there, input capacitor will be placed. Then, the output capacitors. EMI reducing snubber filters are next, followed by the actual control IC and the often forgotten gate drive paths. The last components to be placed are the signal level, or analog parts. Finally, I’ll discuss how to take advantage of multiple layers if you happen to have such luxury, and how to deal with single layouts if you have to deal with that special challenge.
I’m going to take you through all the major parts of routing your PCB. With an eye for the best possible electromagnetic compatibility, or EMC. It really is true that a switcher with all the component values chosen perfectly can fail to work at all, interfere with other circuits, including its own node, or blow up, what veterans call, “Letting the magic smoke out.” All this can occur if the PCB is not designed properly. A well-designed PCB, on the other hand, will provide the best efficiency and lowest noise. Not zero noise, that’s simply not possible, but the lowest noise.
Typical Synchronous Buck Controller
This is a typical data sheet front page schematic. When I was an application engineer writing data sheets, I always the following debate with the marketing engineers while writing the document. I would say, “This schematic should have all the components needed to make the IC work.” Then, the marketeers would say, “Don’t put so many parts on there. The customers will think you need too many expensive components to make it work.”
Circuit schematics, like this example, rarely provide any insight into proper PCB layout, although I have seen some footnotes placed near certain components on various customer designs.
Like many schematics, the pin note shown is not representative of the actual IC, which is a TSSOP-20 with a thermal tab underneath. The compromise was to put more realistic schematics toward the back of the data sheet. For example, the demo board schematic. By the way, the good stuff is always at the back of data sheets, so just don’t read that first page.
A question for you, what is the most important component on this schematic? Hint, it isn’t actually shown. Second hint, this is a trick question. Answer, if you said the PCB is the most important component not shown on this schematic, you’re on your way to becoming a good layout engineer.
There are several names for the ways the components are connected electrically on a PCB. No standard naming exists, and I use the different names interchangeably. Different piece of your layout software also calls these objects by different names. Traces, tracks, and lines are connections of a defined width. Shapes, pours, polygons, and areas are usually drawn by placing the corners. I always, always start by placing the switch node components first. Typically, that’s the inductor or transformer winding, and one or two power switches. The big resistor RCS is for sensing current, and it goes in series with Q2, the synchronous MOSFET. It makes everything harder, but it’s a necessary evil.
Step 1: The Switch Node
The switch node is a great electrostatic radiator, as it swings between B and in-ground at the switching frequency. Displacement currents will flow in an effort to charge and discharge the capaciousness between the switch node and the ground planes in free space. In general, it is better if the area of this node is minimized. I like to start with the power switch diode and inductor that make up the switch node, and place them so that their paths are as close as possible. Then, I put a solid shape that just covers all three paths.
For other than buck regulators, take a look at any nodes that swing through high potentials, and look for ways to minimize capacitance to the rest of the world. Keep in mind that in many typologies, like Flybacks or SEPICS, there will be two switching nodes, and each deserves the same special treatment.
Step 2: Input Capacitor Bank
As discussed earlier, the loop between the input cap, the high-side FET, and the low-side FET needs to be minimized. This is the most critical path in Buck designs. Follow the guidance discussed regarding low-side FET source grounding to the input cap ground, to minimize output spikes. And be sure to use large copper polygons for the main power connections to the MOSFETs. This is helpful not only electrically, but thermally. The same philosophy applies to the use of vias. More is generally better. Just think of all those inductances connected in parallel. They reduce, just like resistors in parallel. Vias also act as thermal passages to the backside and inner layers of the board. Fill them with solder, if possible. While not nearly as good as copper, either electrically or thermally, solder is much better than air, and that’s what would fill the holes unless you have the budget for very special copper plugs.
See how Cin2, that small capacitor, goes in closest to the FETs. That’s the low value MLCC, typically 100 nF, designed to reduce the highest frequency noise and harmonics. It’s small, both in its capacitive value and physical size, to minimize both ESR and ESL. After Cin2, the bigger MLCCs come in. They reduce input voltage and current ripple of the switching frequency and the lower harmonics. We don’t see it on the slide, but the big aluminum or tantalum or polymer bulk would go farthest away off the page towards the left. Recall that this cap dampens potential oscillations and sustains the input voltage during transients, all of which are low, sub switching frequency events, so having this cap farther away is no problem.
Step 3a: Get Snubbers in Tight Loops
If you’re following this seminar series in order, then you’re probably wondering what these snubber filters are for, since I haven’t said much at all about them. Snubbers will get a very thorough treatment in part four of this seminar. So for now, I’ll simply say that they reduce high frequency noise and improve radiated emissions. Because snubbers treat such high frequency noise, usually above 10 megahertz, it’s critical that they go in tight loops with minimum inductance, otherwise they won’t be able to filter anything useful.
Step 3b: Output Capacitor Bank
As we look at the complete layout here, I’d like to add another word of caution to emphasize the point about the low-side FET, or the anode or the diode. This is a noisy node and it should not be connected directly to the ground plane. Doing so will inject noise into the ground plane and corrupt it for the rest of the nodes depending upon it. Think about a rowdy class of five year olds all suddenly let loose on a playground.
If you see spikes for bringing on the output of a buck regulator, this connection was probably made incorrectly. In an ideal design, there would be nearly no spikes at all on the output of a buck regulator. In general, any spikes that do appear on the output are conducted in through the ground rail. With careful attention to the path between the low-side switch grounding, back to the input capacitor, output spikes can be nearly eliminated, or at least greatly reduced, from what is commonly accepted for a switching regulator. Now it seems contradictory, but the output capacitors need less worry. The inductor keeps high frequency currents and these elements to a minimum.
The smallest output capacitor, Co5, goes right near the output connector, or the load, if the load is on the same PCB, to clean up any high frequency noise before it disturbs the load. If high frequency noise gets into the output wiring harness, it will use them as an antennae to radiate. All the more reason to keep Vout nice and clean.
Step 4: Position the IC
The silicon designer, and silicon layout engineer, take the noisy and quiet sides of the actual IC into account in creating its internal circuits. The applications engineer advises them, explaining how a certain pinout will make the PCB layout easier. An IC that is well laid out will group the noisy pins, like the gate drivers, with root strap pins on one side of the IC. Then, the sensitive analog pins, like the control over the feedback node or the soft start go on the other side.
Step 5a: Gate Drive Circuitry
The gate connections to external MOSFETs are very high DIDD paths, and as such need careful thought. Big FETs with lots of gate charge, can induce peak currents of multiple amps. Long connections here will dramatically slow the rise and fall times of the FET switches. This is particularly important for the high side FET in buck applications, since overly slow edges increase the switching loss. Try and lay the gate-to-driver connection directly over the source-to-driver ground connection to minimize the area enclosed by the resulting loop, and use traces of at least 0.3 mm wide. That’s 15 mils for anyone who still likes the imperial system. I almost always have to route my gate drives through two layers, so I make a serious effort to put at least two vias in parallel, having the parasitic inductance in that path.
Step 5b: Complete High Side Gate Drive Path
I see a lot of designs where the layout engineer did a good job of making short, wide, low inductance connections from the gate drive pin to the gate of the MOSFET, but it the high-side MOSFET or the low-side. But then, the return path gets forgotten. That’s why so many slides from sections 3-1 and 3-2 asked you to think about signals as currents that flow in loops.
For the high-side FET, the return path is the switch node. For thermal reasons, the switch node usually has plenty of thermal vias, and these can be used to get the drive current back home. Sometimes, you can run the return path directly underneath the send path. Though in this case, since I was able to route both on the same top layer, I chose to put them close together and in parallel, like the differential pair that they are. Usually, there’s also a bootstrap. That’s the charge pump that generates the fully in drive for the n-MOSFETs, and its diode and capacitor also need short, low conductance loops.
Step 5c: Complete Low Side Gate Drive Path
The low-side, or synchronous MOSFET gate drive’s return path is through system ground. If you just thought, “Hey. Easy,” then hold on a moment. Remember that we’re going to force all the electrons to go where we want them to go. Just plopping down some vias and letting electrons go where they want in the ground net, is not the way to do things. Instead, run a separate trace. A lot of control and regulator ICs have a dedicated ground pin for this. It’s usually called P-ground, or sometimes even more directly, gate return or something similar. The physical connection between all these paths and parts of ground is underneath the IC. As before, use at least two vias when switching between layers, and run those return paths as close as possible to the send paths.
Step 6: Differential Current Sense
Not every control IC has differential sense lines, but it is quite difficult to make a robust IC if you don’t sense at least one of the main currents. This IC senses the current in series with the low-side MOSFET. One unfortunate side effect of that is the big sense resistor. And there’s another challenge, too. Electrically, the negative side of the current sense IC is ground. It is nearly impossible to route differential sense lines on the same layer as the sense resistor, so they have to go through vias. There’s no need to parallel vias this time, since the currents are in the microRAM range, but any solid ground planes will connect to that negative side via, and short out your carefully laid sense line PCB trace.
I’m not so worried about the sense line electrons getting lost on the way home. It’s the bad influence of other noisy currents that may well be in the ground plane. It’s like telling your kids to hurry home after school and not to talk to strangers. It’s generally desirable to tie the controller IC’s A-ground and P-ground, that would be analog ground and power ground, sometimes called signal ground and power ground, or just signal ground and ground. But in any case, to tie them together at a signal point that also ties to the ground plane. More and more ICs, even controllers that don’t directly process the big currents, have a thermal pad underneath the package that is connected electrically to ground. That’s a great place to bring all the analog and power grounds together.
Step 7: Position the Low Power Parts
If you have room for a dedicated topside ground shape, you can use that as a return for all the ground reference control circuits, the feedback divider, the soft start, the control loop. If such a shape won’t fit, use a trace that daisy chains from the AGND pin to the various small signal grounds. If you wanna route this trace through multiple layers, there’ll be a problem with the layout software wanting to tie the via to an internal ground plane. That would just draw the whole point of wanting to segregate this trace. So, I recommend keeping it on the top layer. You wanna find a way to fool your software into doing what you want.
One approach is to come up with a separate AGND symbol. This allows you to tie all the signal ground points together through multiple layers without connecting to the internal plane. However, you may well generate a DRC error when you try and connect the AGND and PGND, or the AGND and PGND nets. In some programs, you simple accept the error and ignore it, knowing full well what it is. Some programs will not allow you to connect the two separate nets on the schematic.
Step 8: Feedback Trace
Follow the grounding suggestions discussed earlier. Keep the highest impedance traces short since they will have the greatest tendency to pick up stray fields. So as an example, the two resistors in a feedback divider should be located very close to the feedback pin of the regulator, not near the power supply’s output. The connection from the top of the divider to the supply output is Vout, a very low impedance connection, and as such, it will be immune to noise pickup. The amplifier input, in contrast, is a very high impedance input and will be very susceptible to stray field induced noise.
There’s a tendency to wanna make sensitive nodes large in the mistaken belief that this will offer some shielding effects. In fact, the opposite is true. This increases the capacitance to free space, and increases the likelihood of noise pickup. Make sensitive traces narrow and as short as possible. This is where you wanna use, for example, 0.2 mm for the width of your tracks and traces.
Step 9 Flood Unused Areas with Copper
My old boss Craig was a real electron psychologist. I swear, he could practically sniff the trail that would take the board. When we finished a design for an EVAL board, back in National Semiconductor, Craig would print out all the layers, one on top of each other, on a sheet of paper and hold them up to the light. If he saw a white space, he’d send us back to rework the design. Quote, “You’ve paid for 100% copper foil,” unquote, he would say, “So get your money’s worth.”
The trick to flooding unused PCB area is to make sure you connect to quiet nodes. Ground is quiet, but your Vin and Vout rails are too. If you watched part two of this seminar on the Buck, you got my full discourse on mixing different types and sizes of capacitors and all the power rails and switching supplies. That makes both Vin and Vout into low impedance nets over a nice, wide frequency range.
The Switch Node Dilemna Revisited
The switching node is so important that our first task on the bottom layer is to review this critical compromise between thermal management and electrical noise. In particular, the low-side MOSFET depends upon some monomer copper mask to keep cool, because its drain connects to the switch node, and most of the heat of a MOSFET comes out of the drain. The footprint for this package, a thermally enhanced SO8, has 12 thermal vias built right in. One technique, which has worked well for me, has been to place a polygon on the bottom layer with the same shape and size as the top layer polygon. The one that just covered the pads of the inductor and the two MOSFETs. A good matrix of thermal vias will help draw heat down to the bottom layer. Even in designs without active cooling, convection will more than likely move some air across the bottom of the PCB.
I’ve debated the pros and cons of interrupting the ground plane for this switch node shape, but I haven’t reached any solid conclusions yet. What I do know is that it really helps to prevent overheating the low-side MOSFET, and if your design burns up before you even get to the EMC lab, then you haven’t gained much.
About Thermal Vias
Here’s the PCB footprint for our 28 pane QF install package with a nice big thermal tab. Thermal vias work best when placed directly underneath a source of heat. But once again, this requires good communication with the PCB manufacturer and your contract manufacturer. My personal experience is that 0.25 mm holes, coupled with 0.5 mm outer diameters, make a great compromise. The holes are too small to wick away much solder, but generally don’t count as so called microvias, which are more expensive to drill. I generally space them either 1 mm, or 1.5 mm, apart.
Just recently, I was surprised by a surcharge on a design I did with vias of this type. That particular PCB manufacturer required a minimum of 0.7 mm outer diameter via in order to drill 0.25 mm holes. So, by your CM a coffee or send a box of chocolates and then ask for their advice. In all seriousness, most operations have great app notes and white papers on the subject of manufacturability.
Step 10: Flood Bottom Side with GND
It’s a very good idea to turn off all the layers except ground at the end of a design, and make sure you still have good ground plane integrity when you’re done laying in all the signal and power line traces, and you’ve dropped a bunch of vias throughout the board. Vias are a necessary evil in many cases, but should be avoided as current carrying elements in the power path, if at all possible. The only time they really become desirable is if they can be used to introduce redundant copper areas to a design, such as an inner layer being hooked in parallel to an outside trace area. Vias are used as heat pipes because they have the ability to conduct topside generated heat to the backside of a PCB. The more vias that can be connected to a hot plane area, the more heat spreading can be achieved.
Something to watch out for when using lots of thermal vias, is that the internal ground planes can get badly cutout and end up with nearly no useful current path. This is particularly likely to occur on very small boards, like voltage regulator modules.
Review After Flooding
Many circuits have connections to ground that should not be shorted out when an area’s flooded. PCB design software is getting more sophisticated, and usually can protect against this. Still, a manual check as shown here, is very much worthwhile.
The ground area, this triangle, is kept separate from both the return path of the low-side FET gate drive, and from the negative connection of the differential current sense line. Everything does connect, of course, but at the power pad underneath the IC.
Four Layer PCBs – What to do with all that luxury?
The diagram above shows my preferred use of four layers when I have the luxury of such a thing. Even when I know I’ve got four layers, I still do my absolute best to connect all the power pads on the top layer and to flood any unused area with copper pours of ground, VIN and Vout. Then, I put a nice, solid ground plane on layer two, just below the top layer. Layer three I split between VIN and Vout, and although I try to avoid this, I sometimes put signal layer traces on this layer. I try to reserve layer four for ground. A lot of my signal level connections go here, too. I do this because if these connections are on internal layers, it gets a lot harder to debug the circuit.
Internal Plane/Layer 1 Should be GND
Being just a little bit closer to the top layer increases the capacitance between layer two ground in the VIN and Vout polygon pours in the top layer. Those small capacitances are free and are great for filtering higher frequency noise because they’re often in the range of 100 pF to 1nF. There’s only one thing I allow to break up my layer two ground plane, and that’s the switching node.
Internal Plane/Layer 2 for VIN and Vout
As with the bottom layer, I put a shape of the same size as the one in the top and bottom layers and connect it with plenty of thermal vias. Everything else is ground, broken up only by the vias for signal traces or thermal management. Adding these large continuous shapes adds more free capaciousness, either between VIN in-ground on the left, or Vout in-ground on the right. They also help to spread and dissipate heat. The cutout for the switch node helps draw heat out of the high-side FET and drain, without letting noise couple capacitively into the other planes.
Single Sided Layouts
Single-sided PCBs are quite common in cost limited AC to DC regulators. For example, your mobile phone charger. But the rapid decrease in the cost of Metal Core PCB, or MCPCB, means that more and more LED driving circuits are placed right onto the MCPCB along with the LEDs. The plunging cost of single layer MCPCB has also led to a rise in the number of power components placed on aluminum core dotter boards. This usually means routing everything in one layer, and usually means few or no vias. 0 ohm shunts are usually used to crossed one connection over the other, but these add both resistance and inductance. So, it’s back to the analysis of heavy switch currents. Avoid placing shunts in these paths. Basically, no shunts in a series with power switches, nor in series with a ground connection between the anode or the diode, and the negative of the input capacitor.
Component Placement Strategy – Rules Of Thumb
- You can put inductance in series with an inductor, but do it on the quiet (output) side, NOT the noisy (switch node) side
- Trace width: 0.75mm per amp for 35 µm thickness copper and 1.5mm per amp for 17.5 µm
- 1 A of DC MAX per via is a good design goal
- Vias to bypass caps should be placed tangent to the pad, two per pad is preferred
Trace inductance in the series with an inductor is not generally much of a concern. It will simply have the effect of increasing the total inductance in the path. In contrast, you don’t want to add a significant amount of capaciousness in parallel with an inductor. That’s the analog of adding inductance in series with a capacitor, and it will cause problems. If you must add some inductance in series with an existing inductor, it’s usually better to make the output path a longer one, so you can minimize the size of that noisy switch node.
We’ve already discussed the use of vias to connect bypass caps to planes. A minimum of one per via connected tangent to each pad is required, two per pad is better, and three is slightly better, but coming down the diminishing returns curve. You can’t have too many, but beyond two, they won’t do much added good. The mantra throughout the board layout needs to be quote, “Minimize stray inductance,” unquote. Treat every high DIDT path as a high frequency RF connection, because it is! You may be inclined to say, “Hey. But, I’m only running it 100 kilohertz.” But the fast edges will have frequency components out to the tens of megahertz, possibly to megahertz. Don’t ever forget that when doing a layout.
My First Eval Board: What NOT to Do!
If all of this seemed like too much to absorb in just one pass, well, that’s the beauty of a prerecorded webinar. Besides multiple viewings, I have another way to raise the spirits of all of you, my viewers. This image of my first EVAL board. I did so many things wrong, I’m amazed that it even regulated the output voltage. To name a few, the analog components are right in the middle making the noisy power currents cross underneath. The two power MOSFETS are way far away from the inductor, making a huge radiating switch node. There aren’t any footprints for small MLCC input capacitors or output capacitors. The gate drive uses long, skinny traces and way too much inductance, and the bootstrap circuit is just as bad. So, cheer up if you layout a switcher and the result was a disaster, because a bit of experience and lots of perseverance will improve your PCBs, too.
Next up: Section 4-1 Switching Edge Control for EMC
The next section on switching edge controls, starts with the fact that even a perfect PCB has unwanted capacitance and inductance. This, combined with the energy stored in the diodes or MOSFETs or other power switches, generates transients and oscillations called spikes and ringing. Before digging deeper, we’ll review a normal situation where an LC oscillation occurs, which is in discontinuous mode, or DCM. With that cleared up, the section will explain why gate resistors can help slow edges and how to select the best values. The last part of section 4-1 introduces the RC snubber circuit for damping resonances and presents two methods for picking the best values.
Part 4-1 of our Power Supply Design series will be available as of April 9, 2018.