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PCB Layout for EMC, Part 2 – Power Supply Design Tutorial Section 3-2

This is part 3-2, a continuation of my personal favorite session of the entire series, where I will talk about PCB design for the best possible electromagnetic compatibility or EMC.

Section 3-2 Agenda

  • Noise transfer – by shared conductors
    • A noise transfer test
  • Accidental antennas
  • Switched current and parasitic inductance
  • Measurement techniques in the lab
  • Routing for noise filtering capacitors
  • Spacing for functional isolation

Part 3-1 concluded by looking at how noise gets from a source to a victim via near field electric and near field magnetic means. So, we’ll start by looking at conductive noise and also look at an example. Then we’ll look at how holes in slots and otherwise solid ground plane or power plane can create antennas that radiate unwanted noise. We’ll review best practices for measuring both currents and voltages in the lab followed by a few slides on how to get most out of filter capacitors, especially for higher frequencies. The last part of this section will discuss functional isolation, meaning the distances required to keep your circuit boards functional in the absence of specific limits set by safety or other standards.


E-Field or M-Field?

  1. Check noise, take a picture
  2. Disconnect the load: no load = no/low current
  3. No current = no M-field
  4. If noise disappears, it was magnetic
  5. If noise remains, it is electric

If you’re like me, you don’t really believe something until you see it with your own eyes. So, here’s a test you can do with the basic lab setup. A DC to DC source, electronic load or even some power resistors, a So scope and a voltage probe. Make sure to use the low inductance spring tip or make your own low inductance tip by wrapping bare wire on the barrel and ground connection of the voltage probe. Details on this are shown later on in section 3-2 and were also given in the Buck seminar.

Take a scope capture of the victim voltage net. If the noise matches the switching frequency of your switching converter that’s already a pretty clear sign of who the guilty party is. But, to determine if the actual noise is a result of electric field or magnetic fields or direct coupling repeat this process for no load or minimal load of your switcher, and then do it again for the maximum load. At no load with barely any current flowing the magnetic fields are practically zero. Not so for electric fields which only need voltages. So, if your noise disappears from the load goes to zero then you have mostly magnetic fields to blame. If the load goes away but the noise remains then it’s more electric fields or conducted things that are to blame.


Conducted Noise

Imagine that you have something sensitive, like the input turn up amp which is single-ended, or ground referenced. That’s the analog part of this diagram here in blue. Now, imagine that a noisy circuit, for example, a switching power supply exists on the same circuit board. To be fair, switchers aren’t the only noisy things on PCBs. The orange circuit labeled “NOISY” could easily be the output from a microcontroller which bounced up and down with very fast edges and megahertz frequencies. If you simply place vias into the ground plane at the negative connections for the loads of analog and noisy then you run a serious risk that the return currents will intermingle. Fast moving electrons from NOISY will get into the signal path for ANALOG and could easily cause problems.

This means that routing your PCB so that the return paths of your signals is critical, be it they sensitive analog ones or noisy power or digital ones. In effect, you want to leave your electrons no choice but the follow the path that you want them to, and that means very careful treatment of your ground planes and power planes.


E-Field or M-Field or Conducted?

Here’s the poor buck converter that I taught you throughout the previous part of this seminar. Now converting 12 volts down to five volts with no load. The voltage probe using the low inductance test fixture is monitoring the output of the control IC’s air amplifier. Which is a GM type amplifier with a relatively high output impedance. Here’s the voltage of that GM amp AC coupled showing a reasonable amount of noise.

Now, the same photo but note that the upper current is eight amps. Finally, the same’s [co 00:03:36] capture but with all that current flowing a bit more noise in the high frequency spikes or PARD noise is visible. However, overall, the difference is minimal. We can conclude then that this portion of the circuit does not suffer from magnetic field interference and that noise present is mostly conducted or electric field noise. Overall, it’s an indication of a well designed PCB.


Accidental Antennas

Switching converters are sources of noise. There’s no avoiding this fact. And switchers emit radiofrequency noise. I knew plenty of engineers who always kept a portable AM or even FM radio in the lab, and one simple way to test for radiated emissions of a new power supply was to see how close you could get the radio to it before the music dissolved into static. PCB layout alone can’t prevent radiated emissions but a good understanding of how noisy currents can get into accidental antennas is a great start.

Just about every signal in the power path of a switching converter has a DC portion. Usually that’s something well known. For example, the input voltage or the output current. Because the inductors cannot have infinite inductance nor can can the capacitors have infinite capacitance there’s always some ripple, or an AC portion. With the fundamental frequency equal to the switching frequency itself. The square waves, trapezoid waves and triangle waves that form most of those ripples have harmonics extending up to many times the switching frequency.

Then there’s a second fundamental noise source, usually called parasitic ringing, or simply, ringing. Spikes or transients are other common names, and the most technical description of this headache is periodic and random deviation, or PARD noise. If you zoom in and measure you’ll almost always find that ringing has a fundamental above 50 megahertz but below one gigahertz putting it firmly in the radiated EMI spectrum with regards to EMC testing.


Accidental Antennas, Part 2

In section 3-1, I stated that one goal of good PCB layout is to force the electrons to flow where we want them to. In this plot the blue area represents a nearly solid ground plane on the bottom layer of a two-sided PCB. The thick red lines represent traces on the TopLayer. And since they are the only path that current can take from the DC-DC converter to the load every electron regardless of frequency has to flow through these traces. After doing their work on the load the electrons are a lot like an office worker after a hard day. They just want to get home by the easiest route possible. This is where a via to ground placed throughout the proper aforethought can cause major problems. Once the current gets into the ground plane the DC and low frequency portions head back, pretty much directly to the via at the negative of the DC to DC source. That’s the path of least resistance.

But, the high frequency current does something different. It’s looking for the path of least inductance, and that means the smallest possible area between the send path and the return path. If it could somehow stick a current probe into the copper of the ground plane we’d see most of the switching ripple and its harmonics as well as all of the parasitic ringing and its harmonics flowing right underneath those TopLayer traces.

You might be thinking, so what? What does it really matter if the route that electrons of different frequencies take is different? As usual, the answer is that it depends.


Accidental Antennas, Part 3

If the ground plane was truly solid and unbroken then it wouldn’t matter so much, but even if you had 16 layers for your PCB and eight of those were dedicated to ground you’d have vias, and vias are holes when high frequency current encounters such an obstacle that goes around, but it also creates an electromagnetic field across the void, and that’s a slot antenna. The dimensions of the hole dictate the frequency of being radiated.

In this diagram the designer kept the ground plane continuous between the two vias that unite the load’s negative with the DC to DC’s negative. But they forgot about the high frequency current. A via placed in the path of the AC current interrupts the flow of those noisy electrons and that generates radiation.


Accidental Antennas, Part 4

A more likely scenario than a small via being in just the wrong spot is a trace in the PCB layer otherwise used as ground. This happens all the time in two-layered designs, not to mention single-layer designs. Now, the AC current has to go around a gap, or actually two gaps of length L, giving rise to radiated EMI at the frequency shown here. Later on, in section 3-3 where we review our PCB designs step by step I’ll discuss the segmentation of a power supply PCB into the noisy section and a quiet, or analog, section. But that isn’t always practical, not to mention that truly dense designs can have components on both sides of the PCB.

Compromise is once again, the key concept. And one compromise for this slide would be moving the trace and the vias on the bottom layer away from the TopLayer trace.


Real Ground Planes Look Like Swiss Cheese

Just to be clear, what I call Swiss cheese is also known as emmental cheese. That mild cheese that has plenty of holes due to air that show up when you slice it. In this design which I did for myself I could have had as many layers as I wanted. In this case I used four and this brown shape is on layer two just below the top layer and it’s all ground except for two shapes on the right. Most of the two switching regulators are also on the right side, and, as you can see the right side is full of holes. It was critical then that I gave every current going out from the source to the load a path to return by low impedance, meaning not only low resistance but low inductance. That’s to say low impedance over a full range of frequencies from DC up to hundreds of megahertz.


Switched Currents and Parasitic L

A match made in h*ll… One simple formula says it all. V=L  di/dt. This is the one my old boss said over and over to minimize stray inductance in the power path.

There’s no avoiding fast edges of both currents and voltages in a switching converter. Even resonant converters which attempt to minimize this still have some fast edges. Whenever these sharp edges meet inductance, even a tiny bit of inductance, voltage noise is created. The switching node is by far the biggest generator of fast edges, both in current and in voltage, and the first pass of pretty much every design has an overshoot transient on the rising edge and and an undershoot transient on the low edge. Here on this slide I’ve drawn those triangle envelopes, but keep in mind in a practice they are sinusoidal oscillations.

One of the most important keys to good PCB design is to prevent these transients from getting into the ground plane. Once they contaminate quote unquote the ground connection these high frequency noise signals will appear virtually everywhere in your PCB. One thing you can do when debugging a PCB is to clip the ground pigtail of a So Scope voltage probe, the closest possible to the pins of whichever switch, or switches, connect to ground. Then, place the probe tip at the ground connection of the input voltage or the output voltage. Part of the signal you will see is radiated noise, but if you see transients in your VN or VL that correspond to the switch node transients then chances are this high frequency noise is everywhere the ground is.


Identifying the High di/dt Loops

We looked at this current loop analysis of a buck regulator in section 3-1. We drew the main loops during the on and off times of the control switch, and concluded that the control MOSFET of a circulating diode need to be placed in the small loops to minimize inductance. But, also that the section of ground extending from the negative of the low side switch back to the negative of the input capacitor was also a path with heavy switch current, aka high di/dt. Now, how can we avoid noise getting into our ground plane since the big trapezoid wave current with lots of harmonics has to float through this section and that trapezoid wave will contain transient same reading as well?


Critical Loop for Buck Converters

One wonderful trick is the route end note of the diode or the source of the low side MOSFET if it’s a synchronous buck back to the negative of the input capacitor on the layer other than the ground plane layer.

I strongly suggest that this be the same layer that the inductor, input capacitor, and power switches are placed on, usually the TopLayer, but you absolutely positively should not do is place a bunch of vias right next to the diode’s anode. If you’re designing the schematics but someone else is going to route their PCB draw the schematic like I’ve done here, and place a note in the text. It won’t take you more than one minute and all the help and insight you can give to the PCB a layout engineer will help them tremendously.

Visualize the electrons, especially the high frequency ones. Force them to flow past the negative of the input capacitor where they’ll be filtered before giving them any chance whatsoever of getting into the ground plane. In my schematic here the input capacitor is shown as one device, but in practice it should be several different ones. The capacitor where the anode should connect to is the smallest lowest value device. That’s the capacitor with the best chance of filtering high frequency noise.

A few years back I was giving this presentation when someone stopped me and said, “The current never flows in that green loop you’ve drawn.” They were right, and this isn’t a current loop. Notice there are no arrows. It’s a physical loop. What I want you to do is to place the MOSFET diode and input capacitor as close as possible together, and minimize the area that connects them.


General Tips and Tricks

There’s science, for example, inductance calculations and then there’s experience. What follows in the next few slides is more experience than science but of course I try to back up my experience with real science whenever possible.

If you already watched section 2-2 then feel free to skip this slide. If not though, then I want to make it absolutely clear what I call a low inductance text fixture. Those little springs that came with. So scope voltage probes are extremely useful but if you lost them or someone else lost them then make your own by wrapping solid 0.5 millimeter diameter bare wire around the exposed barrel of the probe which is ground. Then, with two 90-degree bends up about one centimeter each, you’re ready to probe. I like to take sections of 2.54 millimeter female breakaway headers and snap off pieces of three or four sections, then I cut off the center pins and sod off the outer two pins right across the capacitor, MOSFET or diode. That holds my probe nicely and frees up my hands for other tasks.


Good and Bad Measurement

Here’s the same PCB from before and I’ve got my pink probe, channel three connected with the low inductance test fixture to that input voltage with AC coupling. The blue probe, channel two, is connected to the exact same voltage net, but as the blue circle shows the loop area between the scope tip and the ground pigtail is quite large, and that’s an antenna just waiting to receive some radiated EMI. On the scope screen you can see that the blue channel sees larger transient spikes. Those are the turnon overshoot and turn up undershoot of the control MOSFET. You can also see broadband noise, a sort of fuzz of about 70 millivolts peak to peak. This is radiated noise, not the true conducted signal. In short, trust the pink trace.

Here’s the exact same test, but now I’ve done two things differently. First, I’ve gathered up the ground pigtail and folded it over, decreasing the loop area. And second, I’m also holding the probe tip close to vertically. The previous plot let the PCB hold the probe tip and body, and they were more or less parallel to the PCB. That 70-millivolt fuzz in the blue trace is all but gone, but the transient spikes are even worse. Now, I’d be lying if I said that I’d analyzed the way propagation of the switching frequency harmonics, which generated the fuzz or the wave propagation of the ringing or spikes, but empirically I know that the ringing starts about two orders of magnitude higher in frequency than the switching frequency harmonics. So I’m not surprised to see that its radiation reacts differently to a change in the probe loop geometry.


Placing Wire Loops for Current Probes

A current probe is a must for any serious power supply engineer. In the previous section 3-1, I insisted that signals are currents, not voltages and in general currents are more reliable quantities to measure. But placing a current probe in series with the element you want to measure is a far more serious task than clipping a voltage probe in parallel. For switching converters, the inductors and transformers are often placed between two voltage nets where one is clearly much noisier than the other. This buck converter is a prime example. The switch node on the left bounces up and down by 12 volts, whereas the output voltage on the right hardly moves at all.

This is important because a current probe requires a loop of wire to be inserted and that loop adds inductance. This is fine for inductors and transformers, since the added inductance is very small compared to the inductance of the magnetic element, so the circuit operation is rarely disturbed.


Currents that Defy Measuring

This slide is repeated from the buck, section 2-1. So, if you’ve already seen it feel free to skip ahead. If not, then another very important detail regarding current measurement techniques is knowing which part of a switching converter can’t be measured for current without seriously disrupting their operation. In this slide, I put a loop of wire which has the seemingly innocent quantity of 50 n-henrys of inductance in series with the input capacitors to a buck. But, the circuit reacts by oscillating. It does still function but barely, and no useful data can really be [inaudible 00:15:00] from a circuit with such a heavy oscillation at the input.

In general, don’t try to measure the current of the input or output capacitors nor the power switches, be they diodes or MOSFETs. Instead, diode and MOSFET currents can be inferred by watching inductor or transformer currents, and capacitor currents can usually be inferred by monitoring the input currents, the output currents and the inductor or transformer currents.


Better Low-L Current Measurement

A second technique to try and see a current is to place a sense resistor in series. For this slide I put 10 mohm in series with the same input capacitors and while the circuit oscillates far less the operation is still changed. The ceramic capacitors used have around three mohm of VSR each. So two in parallel would be around 1.5 mohm. Adding 10 mohm as well as the inductance, even out of a tiny 0805-sized thick film resistor causes the oscillation seen in the blue wave form.

But this plot does serve to show us how capacitor current is equal to the input current while the control switch is off. One of the least intrusive but more time consuming way is to check both capacitor and power switch currents is with a good simulation. I certainly don’t advise going directly from simulation to production, but a good simulation is a compliment to lab testing, allows current measurement with no changes to circuit operation.


Routing Bypass Caps On One Layer

On the subject of capacitors, another serious mistake I see from inexperienced PCB designers is to connect bypass capacitors with long thin traces. My definition of a bypass capacitor is one that doesn’t have enough capacitance to sustain the voltage, like the big input and output capacitors do. But instead has a low value and a small size. Small size means low ESR and ESL. Remember, that’s the parasitic inductance. For DC to DC converters bypass caps are ceramic. Almost always the multilayer type called MLCCs. In AC to DC circuits or DC to DC circuits at above 200 volts or so film capacitors are also used.

Long thin traces like the “Terrible!” example on the left had so much inductance that high frequency electrons don’t think twice. They just skip on by. If you route your PCB like that you might as well not even place the capacitor because it’s not gonna do anything. Electrons, especially high frequency ones, need to be forced to flow underneath the solder pads of the bypass capacitors, like I show in the middle. My “Better…” example. Nice thick traces help to reduce inductance and also reduce the loop area between the two nets being filtered. For the best use of your bypass capacitor on the right, get the two connections together as close as the spacing limits will allow. This actually adds capacitance, parasitic capacitance, but beneficial parasitic capacitance between the two voltage nets.

Here again, the TopLayer is red and the bottom layer of the PCB is blue. I still see a lot of circuits where the capacitor is simply connected by a via to a net on a different plane. Via resistance varies with size, but it’s actually the added inductance of vias that causes more problems. In general, it’s best to avoid filtering high frequency noise with capacitors that have to spend two layers using vias. But, in practice there certainly are times when this can’t be avoided.

If you planned on routing like I’ve shown as the “Terrible!” example on the left just save the money and don’t use that capacitor. My better example in the middle uses thicker planes with less loop area, and also gets the VS as close to the solder pads as possible. My best practice example on the right uses two vias in parallel, more to reduce inductance than resistance. But, paralleling of vias helps with both.

Placing them on the interior of the capacitor’s footprint is great electrically, but may pose problems for your PCB manufacturer or, more likely, your contract manufacturer. Vias that are too close to the solder pad may drain away the solder causing voids and poor electrical connections. My recommendation is to develop a good relationship with your PCB makers and assemblers, as they have plenty of experience and will surely tell you what works and what doesn’t.


Spacing for Functional Insulation

I think I spent about two years developing ICs for bucks and boosts and other DC to DC regulators, if I really stop to think about where the chips I was testing were actually going. For the most part, that was into the isolated secondaries of power supplies with an AC to DC front end. Electrical safety standards like IEC60950 for information technology equipment or IEC60598 for leading equipment have very clearly defined minimum spacing for circuits that connect to the AC mains, and for the spacing between primaries and secondaries. But once you’re on the isolated secondary the standards don’t have much to say. So-called functional isolation is just that. The spacing needed to make your circuit functional. Few legally binding limits exist. So, it’s up to the PCB design engineers to find practical guidelines.

Here in the lower left hand corner are the limits set by IEC60950-1. And in my opinion they’re pretty useless. I certainly would not have 0.2 millimeters between two nets with 800 volt transients. The IPC is a consortium based in the United States that has existed since 1957, and it makes nonbinding recommendations for just about every aspect of PCB design. I find the IPC 2221B guidelines to be useful up to around 1,000 volts peak. The goal is to prevent arcing dialectic breakdown of air which usually kills your power supply pretty quickly. But sometimes does so just slowly enough to make you think that nothing is wrong until you of a mountain of field failures. That’s no fun.

I simply have not worked enough at circuits at higher voltages to say with certainty but I understand from colleagues that above around 1,000 volts DC that the distances needed increase exponentially, not linearly.


Based on Typical IC Pin/Pad Pitch

Another practical way to get a feel for the distances needed to prevent arcing is to look at the packages for power devices. Not so much MOSFETs or diodes, since they have few connections, but for the control ICs, the regulators with internal power switches or modules with internal power switches and internal power magnetics. It’s rare to find two pins with less than about 0.2 mm of spacing for voltages up top around 100 volts DC. There are more and more packages where one or more pins have been removed to increase this distance.

For example, regulators for offline circuits up to 800 volts DC or peak often come in DIP-8 packages with pin seven or pin two removed. That provides just over 3 mm of space between a high voltage or pin one or pin eight and the next closest pin.


Next UP: Section 3-3 PCB Layout for EMC, Part 3

Step-by-step PCB layout for a Buck: I believe the step by step example in Section 3-3 is very helpful. We’ll look at reduced schematics from the marketing department as compared to practical ones, and then start with the challenge of the switch node. From there the input capacitors will be placed, then the output capacitors. EMI reducing number of snubber filters are next, followed by the actual control IC and the often forgotten gate drive paths. The last components to be placed will be the signal level or analog parts. Finally, I’ll discuss how to take advantage of multiple layers if you happen to have such luxury. And, how to deal with single-sided layouts if you have to live in poverty.

Link to next section: 3-3 PCB Layout for EMC, Part 3


Link to previous section: 3-1 PCB Layout for EMC, Part 1 

 

 

 

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